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L4 is now a burden

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This commit is contained in:
Youmu Liu
2026-05-20 18:07:21 +08:00
parent 53ed4de530
commit 4694fd9433
1 changed files with 1 additions and 14 deletions
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StgSharp.Common/HighPerformance/Memory/L4.Prefetch.cs
+1 -14
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@@ -96,19 +96,6 @@ namespace StgSharp.HighPerformance.Memory
{
if ((*_predictCount)[index] > short.MaxValue / 2)
{
/*
* EXPERIMENTAL / INTENTIONALLY UNSAFE:
* This code performs a 32-bit atomic operation starting from a short reference.
*
* It is only valid in this specific storage layout because:
* - the runtime is little-endian;
* - arithmetic here does not cause harmful cross-16-bit carry/borrow;
* - the backing storage remains valid and accessible beyond the logical short-array boundary;
* - touching the adjacent 16 bits is acceptable for this allocation layout;
* - misaligned int access is acceptable on the target platform.
*
* This is safe only with the current L4 allocation/layout guarantees.
*/
int predictCount = Volatile.Read(ref (*_predictCount)[index]);
int mapCount = Volatile.Read(ref (*_mapCount)[index]);
int decrement = (int.Min(predictCount, mapCount) + 1) / 2;
@@ -146,7 +133,7 @@ namespace StgSharp.HighPerformance.Memory
(*_mapCount)[index] = 1;
// pre fetch them here
predict.Prefetch(head->Origin, head->Profile, new Span<byte>((byte*)(ulong)head->Address, (int)(ulong)head->SizeForAllocator));
predict.Prefetch(head->Origin, head->Profile, new Span<byte>((byte*)(ulong)head->Position, (int)(ulong)head->SizeForAllocator));
_ = _map.TryAddOrSet(address, (nuint)head, out _);
}
_ = Interlocked.Add(ref _aheadCount, actualCount);