198 lines
8.1 KiB
Markdown
198 lines
8.1 KiB
Markdown
# SIMDID (x86-64) 64-bit Specification (Completed per fixed layout)
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This document completes the **64-bit SIMDID** bit layout as specified, with emphasis on the design of the **AVX512 Feature section ([31..16])**, so it can cover the messy AVX-512 subsets while keeping branching logic compact. It also allocates an **AVX Feature byte** adjacent to the AVX512/AMX regions for AVX-family capabilities.
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> Convention: bit0 is the least significant bit (LSB). Only x86-64 interpreter semantics are defined here; the header’s Root ISA allows extension to other architectures.
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---
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## 1) ASCII Bit Layout (Final)
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```
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SIMDID (64 bits) [63 ........................................................ 0]
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+----------+-----------+----------------+----------------+----------------+----------------+----------------+
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| [63..56] | [47..40] | [39..32] | [31..16] | [15..8] | [7..4] | [3..0] |
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| uArchHi | AVX Feat | AMX Future | AVX512 Feature | MainLevel | Manuf | Root |
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+----------+-----------+----------------+----------------+----------------+----------------+----------------+
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```
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- **[3..0] Root ISA**: Root ISA type (selects interpreter)
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- **[7..4] Manufacture**: Vendor info (Intel/AMD for x86)
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- **[15..8] MainLevel**: Main ISA level (ascending, shared bit semantics)
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- **[31..16] AVX512 Feature**: AVX-512 features/subsets/implementation form (key part)
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- **[39..32] AMX Future**: AMX features (few bits for now)
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- **[47..40] AVX Feature**: AVX-family capabilities (base requires AVX+AVX2; key extensions include FMA/F16C)
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- **[63..56] uArchHi**: Optional microarchitecture/policy hints (default 0, no functional impact).
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---
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## 2) Root ISA ([3..0])
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Suggested encoding (minimal usable set, expandable if needed):
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| Value | Root ISA |
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|---:|----------|
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| 0 | Unknown |
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| 1 | x86-64 |
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| 2 | AArch64 |
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| 3 | PPC64LE |
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| 4 | Apple Silicon (distinct value as required) |
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| 5 | RISC-V |
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| 6 | LoongArch |
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| 7..15 | Reserved |
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> Note: Architecturally Apple Silicon is AArch64; a distinct value is provided here because the Root ISA layer may distinguish it. Interpreter choice is up to implementation.
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---
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## 3) Manufacture ([7..4])
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For **x86-64**:
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| Value | Manufacture |
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|---:|-------------|
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| 0 | Unknown/Other |
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| 1 | Intel |
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| 2 | AMD |
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| 3 | VIA/Zhaoxin |
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| 4..15 | Reserved |
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For other Root ISAs, this nibble is defined by their interpreters (e.g., Apple/Qualcomm/MediaTek for ARM).
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---
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## 4) MainLevel ([15..8], ascending)
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"Shared bits and ascending" means higher values indicate higher capability (or later scheduling order). Suggested values:
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| Value | MainLevel |
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|---:|-----------|
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| 0 | NONE |
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| 1 | SSE (full SSE family: SSE1..SSE4.2) |
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| 2 | AVX2 |
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| 3 | AVX2_FMA |
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| 4 | AVX2_FMA_F16C (from this level onward, 16-bit types are supported) |
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| 5 | AVX512 (check [31..16]) |
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| 6 | AMX |
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| 7 | AVX10 |
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| 8..255 | Reserved |
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> Scheduling suggestion: `MainLevel` is the primary switch; only when `MainLevel >= AVX512` should `AVX512 Feature` be parsed; only when `MainLevel >= AMX` should `AMX Future` be parsed. AVX Feature sits beside AMX/AVX512 and is meaningful when AVX or higher is present.
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---
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## 5) AVX512 Feature ([31..16]) Design Goals (Compact)
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1) **Base AVX512 one-shot check**: Use 1 bit for the bundle `F + CD + VL + DQ + BW`, avoiding multiple subset checks.
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2) **Glue vs native**: Use an implementation field to distinguish `AVX512-DUAL` (glue/downclock risk) from `AVX512-NATIVE` (full 512-bit ALU).
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3) **Niche/AI extensions separated**: VNNI, BF16/FP16, and similar extensions each get a dedicated bit so the base path stays simple.
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---
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## 6) AVX512 Feature Bit Layout ([31..16] = 16 bits, compact)
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AVX512 Feature (bits 31..16)
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| **bit** | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
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|-----------|-----|-----|------|------|------|-------|------|------|-------|-------|----|------|----|----|----|----|
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| **Usage** | R | R | FP16 | BF16 | VNNI | VBMI2 | VBMI | R/AI | Impl1 | Impl0 | R | BASE | R | R | R | R |
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Notes:
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- **BASE (bit 20)**: Base AVX512 bundle, indicating `F + CD + VL + DQ + BW` are all present. If set to 1, the detecting side must guarantee these subsets are all available.
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- **AVX512_IMPL ([23..22], 2-bit)**: Implementation form (width policy).
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| Value | Meaning |
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|---:|------|
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| 0 | Unknown (strategy decided by Manufacture/uArch) |
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| 1 | AVX512-DUAL (glue/downclock risk; prefer 256-bit path) |
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| 2 | AVX512-NATIVE (full 512-bit ALU; 512-bit path is usable) |
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| 3 | Reserved |
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- **VBMI/VBMI2/VNNI/BF16/FP16 ([29..26])**: Commonly needed niche or AI-related small-type extensions; set as needed.
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- **R/AI (bit 24)**: Reserved for future AI or other non-crypto extensions.
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- **[31..30], [21], [19..16]**: Reserved for future allocation.
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---
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## 7) AVX Feature Byte ([47..40], 8 bits)
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Purpose: compact AVX-family capability encoding adjacent to AVX512/AMX. Base requirement: AVX **and** AVX2 present. Key extensions: FMA and F16C. Additional bits reserved for other extensions.
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AVX Feature (bits 47..40)
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| bit | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 |
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|-----|----|----|----|----|----|----|----|----|
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| use | R | R | R | R | F16C | FMA | AVX2 | AVX |
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Rules:
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- **AVX (bit 40)**: AVX present.
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- **AVX2 (bit 41)**: AVX2 present. For the AVX feature byte to be considered valid, both AVX and AVX2 must be set.
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- **FMA (bit 42)**: FMA present.
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- **F16C (bit 43)**: F16C present.
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- **[44..47]**: Reserved for other AVX-family extensions (e.g., BMI/BMI2, IFMA, XOP) as needed.
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---
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## 8) "AVX512BASE" Determination (Single Check)
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- **Rule**: `BASE=1` implies `F+CD+VL+DQ+BW` are all present; no need for per-subset checks. Detection must keep this consistent; if not all subsets are present, set to 0.
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- **Runtime branching**:
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- If `MainLevel < AVX512`: fall back to AVX2/FMA path.
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- Otherwise:
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- Check `BASE`; if 0, fall back to AVX2/FMA (or treat as detection failure).
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- Check `AVX512_IMPL`: `DUAL` uses 256-bit/downclock-safe path, `NATIVE` uses 512-bit path.
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- When small-type/AI capabilities are required, consult `VNNI/BF16/FP16/VBMI/VBMI2` bits.
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---
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## 9) AMX Future ([39..32], 8 bits)
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A single byte is reserved; define three common bits for now, leave the rest reserved:
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| bit (relative to [39..32]) | Name | Note |
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|---:|------|------|
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| 0 | AMX_TILE | Tile base |
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| 1 | AMX_INT8 | INT8 tile |
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| 2 | AMX_BF16 | BF16 tile |
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| 3..7 | Reserved | |
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When `MainLevel < AMX`, this byte can be all zeros.
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---
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## 10) uArchHi ([63..56], 8 bits)
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Purpose: optional high-byte strategy field to address issues like early Intel/AMD "glue" AVX512 that are not expressible purely via CPUID subsets. Defaults to 0.
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Suggested minimal use:
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- `0`: unused
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- `1`: ForceDual (treat as AVX512-DUAL even if impl is unknown)
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- `2`: ForceNative (treat as AVX512-NATIVE even if impl is unknown)
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- `3..`: Implementation-maintained uArch enumeration (e.g., SKX/ICL/SPR/ZEN4/ZEN5…)
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Practical strategy for a single maintainer:
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- AMD: detection side sets `AVX512_IMPL = DUAL` directly (no uArch needed)
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- Intel: enumerate only selected models of interest; otherwise Unknown follows default policy
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---
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## 11) Minimal Detection-Side Fill Rules (x86-64)
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1) Set `RootISA = x86-64`, `Manufacture = Intel/AMD`.
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2) Compute `MainLevel` (per ascending rule).
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3) If `MainLevel >= AVX512`:
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- If `F+CD+VL+DQ+BW` are all present, set `BASE = 1`; otherwise `BASE = 0`.
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- Set `AVX512_IMPL`:
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- AMD: DUAL (per definition)
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- Intel: Decide DUAL/NATIVE based on family/model or policy table; if uncertain, use Unknown
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- When VNNI/BF16/FP16/VBMI/VBMI2 are detected, set the corresponding bits.
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4) If `MainLevel >= AMX`: fill the AMX byte.
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5) When AVX/AVX2 are present, populate the AVX Feature byte: set AVX and AVX2; set FMA and F16C when detected; leave reserved bits for future extensions.
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6) Use uArchHi only when additional policy is needed; otherwise leave as 0.
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---
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## 12) Choice for High Bits Reservation
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Currently `[31..24]` is reserved for AVX512 extensions/AI. `[47..44]` is reserved for AVX-family extensions beside the AVX byte. uArchHi `[63..56]` remains available for minimal policy hints. If IFMA or other extensions are more important, repurpose the reserved bits while keeping `BASE` and `Impl` unchanged. |