1111 lines
32 KiB
Plaintext
1111 lines
32 KiB
Plaintext
; Listing generated by Microsoft (R) Optimizing Compiler Version 19.44.35220.0
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include listing.inc
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INCLUDELIB MSVCRTD
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INCLUDELIB OLDNAMES
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_DATA SEGMENT
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COMM infolog:BYTE:0200H
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_DATA ENDS
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msvcjmc SEGMENT
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__5C8CA4D3_mmintrin@h DB 01H
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__7CD62D9E_malloc@h DB 01H
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__9DCE0DC8_xmmintrin@h DB 01H
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__9DED9ED1_winapifamily@h DB 01H
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__6B04FCB3_specstrings_undef@h DB 01H
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__9FB25DBE_assert@h DB 01H
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__4E664295_glfw_function@h DB 01H
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__64C0EF11_StgSharpNative@h DB 01H
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__E2EC0CAF_sn_matkernel@h DB 01H
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__AA840D82_sn_intrinsic@h DB 01H
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__CE29950A_sn_intrincontext@x86@h DB 01H
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__E2B4C3B7_m@basic@x86@c DB 01H
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msvcjmc ENDS
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PUBLIC float_kernel_transpose_sse
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PUBLIC float_kernel_transpose_avx
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PUBLIC float_kernel_transpose_512
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PUBLIC float_pnl_clear_sse
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PUBLIC float_pnl_clear_avx
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PUBLIC float_pnl_clear_512
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PUBLIC double_pnl_clear_sse
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PUBLIC double_pnl_clear_avx
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PUBLIC double_pnl_clear_512
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PUBLIC __JustMyCode_Default
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PUBLIC __zmm@0000000f0000000b00000007000000030000000e0000000a00000006000000020000000d0000000900000005000000010000000c000000080000000400000000
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EXTRN _RTC_InitBase:PROC
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EXTRN _RTC_Shutdown:PROC
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EXTRN __CheckForDebuggerJustMyCode:PROC
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; COMDAT pdata
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pdata SEGMENT
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$pdata$float_kernel_transpose_sse DD imagerel $LN3
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DD imagerel $LN3+366
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DD imagerel $unwind$float_kernel_transpose_sse
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pdata ENDS
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; COMDAT pdata
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pdata SEGMENT
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$pdata$float_kernel_transpose_avx DD imagerel $LN3
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DD imagerel $LN3+258
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DD imagerel $unwind$float_kernel_transpose_avx
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pdata ENDS
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; COMDAT pdata
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pdata SEGMENT
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$pdata$float_kernel_transpose_512 DD imagerel $LN3
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DD imagerel $LN3+144
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DD imagerel $unwind$float_kernel_transpose_512
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pdata ENDS
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; COMDAT pdata
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pdata SEGMENT
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$pdata$float_pnl_clear_sse DD imagerel $LN6
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DD imagerel $LN6+117
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DD imagerel $unwind$float_pnl_clear_sse
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pdata ENDS
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; COMDAT pdata
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pdata SEGMENT
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$pdata$float_pnl_clear_avx DD imagerel $LN6
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DD imagerel $LN6+134
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DD imagerel $unwind$float_pnl_clear_avx
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pdata ENDS
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; COMDAT pdata
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pdata SEGMENT
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$pdata$float_pnl_clear_512 DD imagerel $LN6
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DD imagerel $LN6+155
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DD imagerel $unwind$float_pnl_clear_512
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pdata ENDS
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; COMDAT pdata
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pdata SEGMENT
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$pdata$double_pnl_clear_sse DD imagerel $LN3
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DD imagerel $LN3+205
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DD imagerel $unwind$double_pnl_clear_sse
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pdata ENDS
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; COMDAT pdata
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pdata SEGMENT
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$pdata$double_pnl_clear_avx DD imagerel $LN6
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DD imagerel $LN6+134
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DD imagerel $unwind$double_pnl_clear_avx
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pdata ENDS
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; COMDAT pdata
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pdata SEGMENT
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$pdata$double_pnl_clear_512 DD imagerel $LN6
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DD imagerel $LN6+155
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DD imagerel $unwind$double_pnl_clear_512
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pdata ENDS
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; COMDAT __zmm@0000000f0000000b00000007000000030000000e0000000a00000006000000020000000d0000000900000005000000010000000c000000080000000400000000
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CONST SEGMENT
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__zmm@0000000f0000000b00000007000000030000000e0000000a00000006000000020000000d0000000900000005000000010000000c000000080000000400000000 DB 00H
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DB 00H, 00H, 00H, 04H, 00H, 00H, 00H, 08H, 00H, 00H, 00H, 0cH, 00H
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DB 00H, 00H, 01H, 00H, 00H, 00H, 05H, 00H, 00H, 00H, 09H, 00H, 00H
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DB 00H, 0dH, 00H, 00H, 00H, 02H, 00H, 00H, 00H, 06H, 00H, 00H, 00H
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DB 0aH, 00H, 00H, 00H, 0eH, 00H, 00H, 00H, 03H, 00H, 00H, 00H, 07H
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DB 00H, 00H, 00H, 0bH, 00H, 00H, 00H, 0fH, 00H, 00H, 00H
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CONST ENDS
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; COMDAT rtc$TMZ
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rtc$TMZ SEGMENT
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_RTC_Shutdown.rtc$TMZ DQ FLAT:_RTC_Shutdown
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rtc$TMZ ENDS
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; COMDAT rtc$IMZ
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rtc$IMZ SEGMENT
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_RTC_InitBase.rtc$IMZ DQ FLAT:_RTC_InitBase
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rtc$IMZ ENDS
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; COMDAT xdata
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xdata SEGMENT
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$unwind$double_pnl_clear_512 DD 02d061e01H
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DD 01102315H
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DD 07009003aH
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DD 0d0075008H
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xdata ENDS
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; COMDAT xdata
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xdata SEGMENT
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$unwind$double_pnl_clear_avx DD 02d061e01H
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DD 01102315H
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DD 07009002eH
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DD 0d0075008H
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xdata ENDS
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; COMDAT xdata
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xdata SEGMENT
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$unwind$double_pnl_clear_sse DD 025051301H
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DD 010e2313H
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DD 070070023H
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DD 05006H
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xdata ENDS
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; COMDAT xdata
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xdata SEGMENT
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$unwind$float_pnl_clear_512 DD 02d061e01H
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DD 01102315H
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DD 07009003aH
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DD 0d0075008H
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xdata ENDS
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; COMDAT xdata
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xdata SEGMENT
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$unwind$float_pnl_clear_avx DD 02d061e01H
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DD 01102315H
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DD 07009002eH
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DD 0d0075008H
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xdata ENDS
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; COMDAT xdata
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xdata SEGMENT
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$unwind$float_pnl_clear_sse DD 025051301H
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DD 010e2313H
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DD 070070027H
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DD 05006H
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xdata ENDS
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; COMDAT xdata
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xdata SEGMENT
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$unwind$float_kernel_transpose_512 DD 02d062301H
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DD 0115231aH
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DD 0700e0046H
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DD 0d00c500dH
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xdata ENDS
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; COMDAT xdata
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xdata SEGMENT
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$unwind$float_kernel_transpose_avx DD 02d062301H
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DD 0115231aH
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DD 0700e0042H
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DD 0d00c500dH
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xdata ENDS
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; COMDAT xdata
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xdata SEGMENT
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$unwind$float_kernel_transpose_sse DD 025051801H
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DD 01132318H
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DD 0700c004dH
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DD 0500bH
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xdata ENDS
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; Function compile flags: /Odt
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; COMDAT __JustMyCode_Default
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_TEXT SEGMENT
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__JustMyCode_Default PROC ; COMDAT
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00000 c2 00 00 ret 0
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__JustMyCode_Default ENDP
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_TEXT ENDS
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; Function compile flags: /Odtp /RTCsu /ZI
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; File D:\platform-dev\StgSharp.Native\sn-src\m.basic.x86.c
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; COMDAT double_pnl_clear_512
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_TEXT SEGMENT
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zero$ = 64
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i$1 = 152
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ans$ = 464
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double_pnl_clear_512 PROC ; COMDAT
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; 50 : {
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$LN6:
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00000 48 89 4c 24 08 mov QWORD PTR [rsp+8], rcx
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00005 41 55 push r13
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00007 55 push rbp
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00008 57 push rdi
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00009 48 81 ec d0 01
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00 00 sub rsp, 464 ; 000001d0H
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00010 4c 8d 6c 24 20 lea r13, QWORD PTR [rsp+32]
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00015 48 8d 6c 24 60 lea rbp, QWORD PTR [rsp+96]
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0001a 48 83 e5 c0 and rbp, -64 ; ffffffffffffffc0H
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0001e 48 8d 0d 00 00
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00 00 lea rcx, OFFSET FLAT:__E2B4C3B7_m@basic@x86@c
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00025 e8 00 00 00 00 call __CheckForDebuggerJustMyCode
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0002a 90 npad 1
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; 51 : register __m512 zero = _mm512_setzero_ps();
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0002b c5 f8 57 c0 vxorps xmm0, xmm0, xmm0
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0002f 62 f1 7c 48 11
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45 01 vmovups ZMMWORD PTR zero$[rbp], zmm0
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; 52 : for (size_t i = 0; i < 16; i++) {
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00036 48 c7 85 98 00
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00 00 00 00 00
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00 mov QWORD PTR i$1[rbp], 0
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00041 eb 11 jmp SHORT $LN4@double_pnl
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$LN2@double_pnl:
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00043 48 8b 85 98 00
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00 00 mov rax, QWORD PTR i$1[rbp]
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0004a 48 ff c0 inc rax
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0004d 48 89 85 98 00
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00 00 mov QWORD PTR i$1[rbp], rax
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$LN4@double_pnl:
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00054 48 83 bd 98 00
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00 00 10 cmp QWORD PTR i$1[rbp], 16
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0005c 73 31 jae SHORT $LN3@double_pnl
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; 53 : PANEL_COL_VEC((*ans), i, 0) = zero;
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0005e 48 63 85 98 00
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00 00 movsxd rax, DWORD PTR i$1[rbp]
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00065 48 6b c0 40 imul rax, rax, 64 ; 00000040H
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00069 49 8b 8d d0 01
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00 00 mov rcx, QWORD PTR ans$[r13]
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00070 48 03 c8 add rcx, rax
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00073 48 8b c1 mov rax, rcx
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00076 b9 40 00 00 00 mov ecx, 64 ; 00000040H
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0007b 48 6b c9 00 imul rcx, rcx, 0
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0007f 62 f1 7c 48 10
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45 01 vmovups zmm0, ZMMWORD PTR zero$[rbp]
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00086 62 f1 7c 48 11
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04 08 vmovups ZMMWORD PTR [rax+rcx], zmm0
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; 54 : }
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0008d eb b4 jmp SHORT $LN2@double_pnl
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$LN3@double_pnl:
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; 55 : }
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0008f 49 8d a5 b0 01
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00 00 lea rsp, QWORD PTR [r13+432]
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00096 5f pop rdi
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00097 5d pop rbp
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00098 41 5d pop r13
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0009a c3 ret 0
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double_pnl_clear_512 ENDP
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_TEXT ENDS
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; Function compile flags: /Odtp /RTCsu /ZI
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; File D:\platform-dev\StgSharp.Native\sn-src\m.basic.x86.c
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; COMDAT double_pnl_clear_avx
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_TEXT SEGMENT
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zero$ = 32
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i$1 = 88
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ans$ = 368
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double_pnl_clear_avx PROC ; COMDAT
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; 42 : {
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$LN6:
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00000 48 89 4c 24 08 mov QWORD PTR [rsp+8], rcx
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00005 41 55 push r13
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00007 55 push rbp
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00008 57 push rdi
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00009 48 81 ec 70 01
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00 00 sub rsp, 368 ; 00000170H
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00010 4c 8d 6c 24 20 lea r13, QWORD PTR [rsp+32]
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00015 48 8d 6c 24 40 lea rbp, QWORD PTR [rsp+64]
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0001a 48 83 e5 e0 and rbp, -32 ; ffffffffffffffe0H
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0001e 48 8d 0d 00 00
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00 00 lea rcx, OFFSET FLAT:__E2B4C3B7_m@basic@x86@c
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00025 e8 00 00 00 00 call __CheckForDebuggerJustMyCode
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0002a 90 npad 1
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; 43 : register __m256 zero = _mm256_setzero_ps();
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0002b c5 f8 57 c0 vxorps xmm0, xmm0, xmm0
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0002f c5 fc 11 45 20 vmovups YMMWORD PTR zero$[rbp], ymm0
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; 44 : for (size_t i = 0; i < 8; i++) {
|
|
|
|
00034 48 c7 45 58 00
|
|
00 00 00 mov QWORD PTR i$1[rbp], 0
|
|
0003c eb 0b jmp SHORT $LN4@double_pnl
|
|
$LN2@double_pnl:
|
|
0003e 48 8b 45 58 mov rax, QWORD PTR i$1[rbp]
|
|
00042 48 ff c0 inc rax
|
|
00045 48 89 45 58 mov QWORD PTR i$1[rbp], rax
|
|
$LN4@double_pnl:
|
|
00049 48 83 7d 58 08 cmp QWORD PTR i$1[rbp], 8
|
|
0004e 73 2a jae SHORT $LN3@double_pnl
|
|
|
|
; 45 : PANEL_COL_VEC((*ans), i, 0) = zero;
|
|
|
|
00050 48 63 45 58 movsxd rax, DWORD PTR i$1[rbp]
|
|
00054 48 6b c0 20 imul rax, rax, 32 ; 00000020H
|
|
00058 49 8b 8d 70 01
|
|
00 00 mov rcx, QWORD PTR ans$[r13]
|
|
0005f 48 03 c8 add rcx, rax
|
|
00062 48 8b c1 mov rax, rcx
|
|
00065 b9 20 00 00 00 mov ecx, 32 ; 00000020H
|
|
0006a 48 6b c9 00 imul rcx, rcx, 0
|
|
0006e c5 fc 10 45 20 vmovups ymm0, YMMWORD PTR zero$[rbp]
|
|
00073 c5 fc 11 04 08 vmovups YMMWORD PTR [rax+rcx], ymm0
|
|
|
|
; 46 : }
|
|
|
|
00078 eb c4 jmp SHORT $LN2@double_pnl
|
|
$LN3@double_pnl:
|
|
|
|
; 47 : }
|
|
|
|
0007a 49 8d a5 50 01
|
|
00 00 lea rsp, QWORD PTR [r13+336]
|
|
00081 5f pop rdi
|
|
00082 5d pop rbp
|
|
00083 41 5d pop r13
|
|
00085 c3 ret 0
|
|
double_pnl_clear_avx ENDP
|
|
_TEXT ENDS
|
|
; Function compile flags: /Odtp /RTCsu /ZI
|
|
; File D:\platform-dev\StgSharp.Native\sn-src\m.basic.x86.c
|
|
; COMDAT double_pnl_clear_sse
|
|
_TEXT SEGMENT
|
|
zero$ = 16
|
|
ans$ = 272
|
|
double_pnl_clear_sse PROC ; COMDAT
|
|
|
|
; 33 : {
|
|
|
|
$LN3:
|
|
00000 48 89 4c 24 08 mov QWORD PTR [rsp+8], rcx
|
|
00005 55 push rbp
|
|
00006 57 push rdi
|
|
00007 48 81 ec 18 01
|
|
00 00 sub rsp, 280 ; 00000118H
|
|
0000e 48 8d 6c 24 20 lea rbp, QWORD PTR [rsp+32]
|
|
00013 48 8d 0d 00 00
|
|
00 00 lea rcx, OFFSET FLAT:__E2B4C3B7_m@basic@x86@c
|
|
0001a e8 00 00 00 00 call __CheckForDebuggerJustMyCode
|
|
0001f 90 npad 1
|
|
|
|
; 34 : register __m128 zero = _mm_setzero_ps();
|
|
|
|
00020 0f 57 c0 xorps xmm0, xmm0
|
|
00023 0f 29 45 10 movaps XMMWORD PTR zero$[rbp], xmm0
|
|
|
|
; 35 : PANEL_COL_VEC((*ans), 0, 0) = zero;
|
|
|
|
00027 b8 20 00 00 00 mov eax, 32 ; 00000020H
|
|
0002c 48 6b c0 00 imul rax, rax, 0
|
|
00030 48 8b 8d 10 01
|
|
00 00 mov rcx, QWORD PTR ans$[rbp]
|
|
00037 48 03 c8 add rcx, rax
|
|
0003a 48 8b c1 mov rax, rcx
|
|
0003d b9 10 00 00 00 mov ecx, 16
|
|
00042 48 6b c9 00 imul rcx, rcx, 0
|
|
00046 0f 28 45 10 movaps xmm0, XMMWORD PTR zero$[rbp]
|
|
0004a 0f 11 04 08 movups XMMWORD PTR [rax+rcx], xmm0
|
|
|
|
; 36 : PANEL_COL_VEC((*ans), 1, 0) = zero;
|
|
|
|
0004e b8 20 00 00 00 mov eax, 32 ; 00000020H
|
|
00053 48 6b c0 01 imul rax, rax, 1
|
|
00057 48 8b 8d 10 01
|
|
00 00 mov rcx, QWORD PTR ans$[rbp]
|
|
0005e 48 03 c8 add rcx, rax
|
|
00061 48 8b c1 mov rax, rcx
|
|
00064 b9 10 00 00 00 mov ecx, 16
|
|
00069 48 6b c9 00 imul rcx, rcx, 0
|
|
0006d 0f 28 45 10 movaps xmm0, XMMWORD PTR zero$[rbp]
|
|
00071 0f 11 04 08 movups XMMWORD PTR [rax+rcx], xmm0
|
|
|
|
; 37 : PANEL_COL_VEC((*ans), 2, 0) = zero;
|
|
|
|
00075 b8 20 00 00 00 mov eax, 32 ; 00000020H
|
|
0007a 48 6b c0 02 imul rax, rax, 2
|
|
0007e 48 8b 8d 10 01
|
|
00 00 mov rcx, QWORD PTR ans$[rbp]
|
|
00085 48 03 c8 add rcx, rax
|
|
00088 48 8b c1 mov rax, rcx
|
|
0008b b9 10 00 00 00 mov ecx, 16
|
|
00090 48 6b c9 00 imul rcx, rcx, 0
|
|
00094 0f 28 45 10 movaps xmm0, XMMWORD PTR zero$[rbp]
|
|
00098 0f 11 04 08 movups XMMWORD PTR [rax+rcx], xmm0
|
|
|
|
; 38 : PANEL_COL_VEC((*ans), 3, 0) = zero;
|
|
|
|
0009c b8 20 00 00 00 mov eax, 32 ; 00000020H
|
|
000a1 48 6b c0 03 imul rax, rax, 3
|
|
000a5 48 8b 8d 10 01
|
|
00 00 mov rcx, QWORD PTR ans$[rbp]
|
|
000ac 48 03 c8 add rcx, rax
|
|
000af 48 8b c1 mov rax, rcx
|
|
000b2 b9 10 00 00 00 mov ecx, 16
|
|
000b7 48 6b c9 00 imul rcx, rcx, 0
|
|
000bb 0f 28 45 10 movaps xmm0, XMMWORD PTR zero$[rbp]
|
|
000bf 0f 11 04 08 movups XMMWORD PTR [rax+rcx], xmm0
|
|
|
|
; 39 : }
|
|
|
|
000c3 48 8d a5 f8 00
|
|
00 00 lea rsp, QWORD PTR [rbp+248]
|
|
000ca 5f pop rdi
|
|
000cb 5d pop rbp
|
|
000cc c3 ret 0
|
|
double_pnl_clear_sse ENDP
|
|
_TEXT ENDS
|
|
; Function compile flags: /Odtp /RTCsu /ZI
|
|
; File D:\platform-dev\StgSharp.Native\sn-src\m.basic.x86.c
|
|
; COMDAT float_pnl_clear_512
|
|
_TEXT SEGMENT
|
|
zero$ = 64
|
|
i$1 = 152
|
|
ans$ = 464
|
|
float_pnl_clear_512 PROC ; COMDAT
|
|
|
|
; 25 : {
|
|
|
|
$LN6:
|
|
00000 48 89 4c 24 08 mov QWORD PTR [rsp+8], rcx
|
|
00005 41 55 push r13
|
|
00007 55 push rbp
|
|
00008 57 push rdi
|
|
00009 48 81 ec d0 01
|
|
00 00 sub rsp, 464 ; 000001d0H
|
|
00010 4c 8d 6c 24 20 lea r13, QWORD PTR [rsp+32]
|
|
00015 48 8d 6c 24 60 lea rbp, QWORD PTR [rsp+96]
|
|
0001a 48 83 e5 c0 and rbp, -64 ; ffffffffffffffc0H
|
|
0001e 48 8d 0d 00 00
|
|
00 00 lea rcx, OFFSET FLAT:__E2B4C3B7_m@basic@x86@c
|
|
00025 e8 00 00 00 00 call __CheckForDebuggerJustMyCode
|
|
0002a 90 npad 1
|
|
|
|
; 26 : register __m512 zero = _mm512_setzero_ps();
|
|
|
|
0002b c5 f8 57 c0 vxorps xmm0, xmm0, xmm0
|
|
0002f 62 f1 7c 48 11
|
|
45 01 vmovups ZMMWORD PTR zero$[rbp], zmm0
|
|
|
|
; 27 : for (size_t i = 0; i < 16; i++) {
|
|
|
|
00036 48 c7 85 98 00
|
|
00 00 00 00 00
|
|
00 mov QWORD PTR i$1[rbp], 0
|
|
00041 eb 11 jmp SHORT $LN4@float_pnl_
|
|
$LN2@float_pnl_:
|
|
00043 48 8b 85 98 00
|
|
00 00 mov rax, QWORD PTR i$1[rbp]
|
|
0004a 48 ff c0 inc rax
|
|
0004d 48 89 85 98 00
|
|
00 00 mov QWORD PTR i$1[rbp], rax
|
|
$LN4@float_pnl_:
|
|
00054 48 83 bd 98 00
|
|
00 00 10 cmp QWORD PTR i$1[rbp], 16
|
|
0005c 73 31 jae SHORT $LN3@float_pnl_
|
|
|
|
; 28 : PANEL_COL_VEC((*ans), i, 0) = zero;
|
|
|
|
0005e 48 63 85 98 00
|
|
00 00 movsxd rax, DWORD PTR i$1[rbp]
|
|
00065 48 6b c0 40 imul rax, rax, 64 ; 00000040H
|
|
00069 49 8b 8d d0 01
|
|
00 00 mov rcx, QWORD PTR ans$[r13]
|
|
00070 48 03 c8 add rcx, rax
|
|
00073 48 8b c1 mov rax, rcx
|
|
00076 b9 40 00 00 00 mov ecx, 64 ; 00000040H
|
|
0007b 48 6b c9 00 imul rcx, rcx, 0
|
|
0007f 62 f1 7c 48 10
|
|
45 01 vmovups zmm0, ZMMWORD PTR zero$[rbp]
|
|
00086 62 f1 7c 48 11
|
|
04 08 vmovups ZMMWORD PTR [rax+rcx], zmm0
|
|
|
|
; 29 : }
|
|
|
|
0008d eb b4 jmp SHORT $LN2@float_pnl_
|
|
$LN3@float_pnl_:
|
|
|
|
; 30 : }
|
|
|
|
0008f 49 8d a5 b0 01
|
|
00 00 lea rsp, QWORD PTR [r13+432]
|
|
00096 5f pop rdi
|
|
00097 5d pop rbp
|
|
00098 41 5d pop r13
|
|
0009a c3 ret 0
|
|
float_pnl_clear_512 ENDP
|
|
_TEXT ENDS
|
|
; Function compile flags: /Odtp /RTCsu /ZI
|
|
; File D:\platform-dev\StgSharp.Native\sn-src\m.basic.x86.c
|
|
; COMDAT float_pnl_clear_avx
|
|
_TEXT SEGMENT
|
|
zero$ = 32
|
|
i$1 = 88
|
|
ans$ = 368
|
|
float_pnl_clear_avx PROC ; COMDAT
|
|
|
|
; 17 : {
|
|
|
|
$LN6:
|
|
00000 48 89 4c 24 08 mov QWORD PTR [rsp+8], rcx
|
|
00005 41 55 push r13
|
|
00007 55 push rbp
|
|
00008 57 push rdi
|
|
00009 48 81 ec 70 01
|
|
00 00 sub rsp, 368 ; 00000170H
|
|
00010 4c 8d 6c 24 20 lea r13, QWORD PTR [rsp+32]
|
|
00015 48 8d 6c 24 40 lea rbp, QWORD PTR [rsp+64]
|
|
0001a 48 83 e5 e0 and rbp, -32 ; ffffffffffffffe0H
|
|
0001e 48 8d 0d 00 00
|
|
00 00 lea rcx, OFFSET FLAT:__E2B4C3B7_m@basic@x86@c
|
|
00025 e8 00 00 00 00 call __CheckForDebuggerJustMyCode
|
|
0002a 90 npad 1
|
|
|
|
; 18 : register __m256 zero = _mm256_setzero_ps();
|
|
|
|
0002b c5 f8 57 c0 vxorps xmm0, xmm0, xmm0
|
|
0002f c5 fc 11 45 20 vmovups YMMWORD PTR zero$[rbp], ymm0
|
|
|
|
; 19 : for (size_t i = 0; i < 8; i++) {
|
|
|
|
00034 48 c7 45 58 00
|
|
00 00 00 mov QWORD PTR i$1[rbp], 0
|
|
0003c eb 0b jmp SHORT $LN4@float_pnl_
|
|
$LN2@float_pnl_:
|
|
0003e 48 8b 45 58 mov rax, QWORD PTR i$1[rbp]
|
|
00042 48 ff c0 inc rax
|
|
00045 48 89 45 58 mov QWORD PTR i$1[rbp], rax
|
|
$LN4@float_pnl_:
|
|
00049 48 83 7d 58 08 cmp QWORD PTR i$1[rbp], 8
|
|
0004e 73 2a jae SHORT $LN3@float_pnl_
|
|
|
|
; 20 : PANEL_COL_VEC((*ans), i, 0) = zero;
|
|
|
|
00050 48 63 45 58 movsxd rax, DWORD PTR i$1[rbp]
|
|
00054 48 6b c0 20 imul rax, rax, 32 ; 00000020H
|
|
00058 49 8b 8d 70 01
|
|
00 00 mov rcx, QWORD PTR ans$[r13]
|
|
0005f 48 03 c8 add rcx, rax
|
|
00062 48 8b c1 mov rax, rcx
|
|
00065 b9 20 00 00 00 mov ecx, 32 ; 00000020H
|
|
0006a 48 6b c9 00 imul rcx, rcx, 0
|
|
0006e c5 fc 10 45 20 vmovups ymm0, YMMWORD PTR zero$[rbp]
|
|
00073 c5 fc 11 04 08 vmovups YMMWORD PTR [rax+rcx], ymm0
|
|
|
|
; 21 : }
|
|
|
|
00078 eb c4 jmp SHORT $LN2@float_pnl_
|
|
$LN3@float_pnl_:
|
|
|
|
; 22 : }
|
|
|
|
0007a 49 8d a5 50 01
|
|
00 00 lea rsp, QWORD PTR [r13+336]
|
|
00081 5f pop rdi
|
|
00082 5d pop rbp
|
|
00083 41 5d pop r13
|
|
00085 c3 ret 0
|
|
float_pnl_clear_avx ENDP
|
|
_TEXT ENDS
|
|
; Function compile flags: /Odtp /RTCsu /ZI
|
|
; File D:\platform-dev\StgSharp.Native\sn-src\m.basic.x86.c
|
|
; COMDAT float_pnl_clear_sse
|
|
_TEXT SEGMENT
|
|
zero$ = 16
|
|
i$1 = 56
|
|
ans$ = 304
|
|
float_pnl_clear_sse PROC ; COMDAT
|
|
|
|
; 9 : {
|
|
|
|
$LN6:
|
|
00000 48 89 4c 24 08 mov QWORD PTR [rsp+8], rcx
|
|
00005 55 push rbp
|
|
00006 57 push rdi
|
|
00007 48 81 ec 38 01
|
|
00 00 sub rsp, 312 ; 00000138H
|
|
0000e 48 8d 6c 24 20 lea rbp, QWORD PTR [rsp+32]
|
|
00013 48 8d 0d 00 00
|
|
00 00 lea rcx, OFFSET FLAT:__E2B4C3B7_m@basic@x86@c
|
|
0001a e8 00 00 00 00 call __CheckForDebuggerJustMyCode
|
|
0001f 90 npad 1
|
|
|
|
; 10 : register __m128 zero = _mm_setzero_ps();
|
|
|
|
00020 0f 57 c0 xorps xmm0, xmm0
|
|
00023 0f 29 45 10 movaps XMMWORD PTR zero$[rbp], xmm0
|
|
|
|
; 11 : for (size_t i = 0; i < 4; i++) {
|
|
|
|
00027 48 c7 45 38 00
|
|
00 00 00 mov QWORD PTR i$1[rbp], 0
|
|
0002f eb 0b jmp SHORT $LN4@float_pnl_
|
|
$LN2@float_pnl_:
|
|
00031 48 8b 45 38 mov rax, QWORD PTR i$1[rbp]
|
|
00035 48 ff c0 inc rax
|
|
00038 48 89 45 38 mov QWORD PTR i$1[rbp], rax
|
|
$LN4@float_pnl_:
|
|
0003c 48 83 7d 38 04 cmp QWORD PTR i$1[rbp], 4
|
|
00041 73 28 jae SHORT $LN3@float_pnl_
|
|
|
|
; 12 : PANEL_COL_VEC((*ans), i, 0) = zero;
|
|
|
|
00043 48 63 45 38 movsxd rax, DWORD PTR i$1[rbp]
|
|
00047 48 6b c0 10 imul rax, rax, 16
|
|
0004b 48 8b 8d 30 01
|
|
00 00 mov rcx, QWORD PTR ans$[rbp]
|
|
00052 48 03 c8 add rcx, rax
|
|
00055 48 8b c1 mov rax, rcx
|
|
00058 b9 10 00 00 00 mov ecx, 16
|
|
0005d 48 6b c9 00 imul rcx, rcx, 0
|
|
00061 0f 28 45 10 movaps xmm0, XMMWORD PTR zero$[rbp]
|
|
00065 0f 11 04 08 movups XMMWORD PTR [rax+rcx], xmm0
|
|
|
|
; 13 : }
|
|
|
|
00069 eb c6 jmp SHORT $LN2@float_pnl_
|
|
$LN3@float_pnl_:
|
|
|
|
; 14 : }
|
|
|
|
0006b 48 8d a5 18 01
|
|
00 00 lea rsp, QWORD PTR [rbp+280]
|
|
00072 5f pop rdi
|
|
00073 5d pop rbp
|
|
00074 c3 ret 0
|
|
float_pnl_clear_sse ENDP
|
|
_TEXT ENDS
|
|
; Function compile flags: /Odtp /RTCsu /ZI
|
|
; File D:\platform-dev\StgSharp.Native\sn-src\m.basic.x86.c
|
|
; COMDAT float_kernel_transpose_512
|
|
_TEXT SEGMENT
|
|
matrix$ = 64
|
|
transpose_indices$ = 192
|
|
right$ = 560
|
|
ans$ = 568
|
|
float_kernel_transpose_512 PROC ; COMDAT
|
|
|
|
; 91 : {
|
|
|
|
$LN3:
|
|
00000 48 89 54 24 10 mov QWORD PTR [rsp+16], rdx
|
|
00005 48 89 4c 24 08 mov QWORD PTR [rsp+8], rcx
|
|
0000a 41 55 push r13
|
|
0000c 55 push rbp
|
|
0000d 57 push rdi
|
|
0000e 48 81 ec 30 02
|
|
00 00 sub rsp, 560 ; 00000230H
|
|
00015 4c 8d 6c 24 20 lea r13, QWORD PTR [rsp+32]
|
|
0001a 48 8d 6c 24 60 lea rbp, QWORD PTR [rsp+96]
|
|
0001f 48 83 e5 c0 and rbp, -64 ; ffffffffffffffc0H
|
|
00023 48 8d 0d 00 00
|
|
00 00 lea rcx, OFFSET FLAT:__E2B4C3B7_m@basic@x86@c
|
|
0002a e8 00 00 00 00 call __CheckForDebuggerJustMyCode
|
|
0002f 90 npad 1
|
|
|
|
; 92 : register __m512 matrix = right->f32_z[0];
|
|
|
|
00030 b8 40 00 00 00 mov eax, 64 ; 00000040H
|
|
00035 48 6b c0 00 imul rax, rax, 0
|
|
00039 49 8b 8d 30 02
|
|
00 00 mov rcx, QWORD PTR right$[r13]
|
|
00040 62 f1 7c 48 10
|
|
04 01 vmovups zmm0, ZMMWORD PTR [rcx+rax]
|
|
00047 62 f1 7c 48 11
|
|
45 01 vmovups ZMMWORD PTR matrix$[rbp], zmm0
|
|
|
|
; 93 :
|
|
; 94 : const __m512i transpose_indices =
|
|
|
|
0004e 62 f1 7e 48 6f
|
|
05 00 00 00 00 vmovdqu32 zmm0, ZMMWORD PTR __zmm@0000000f0000000b00000007000000030000000e0000000a00000006000000020000000d0000000900000005000000010000000c000000080000000400000000
|
|
00058 62 f1 7e 48 7f
|
|
45 03 vmovdqu32 ZMMWORD PTR transpose_indices$[rbp], zmm0
|
|
|
|
; 95 : _mm512_setr_epi32(0, 4, 8, 12, 1, 5, 9, 13, 2, 6, 10, 14, 3, 7, 11, 15);
|
|
; 96 :
|
|
; 97 : ans->f32_z[0] = _mm512_permutexvar_ps(transpose_indices, matrix);
|
|
|
|
0005f 62 f1 7e 48 6f
|
|
45 03 vmovdqu32 zmm0, ZMMWORD PTR transpose_indices$[rbp]
|
|
00066 62 f2 7d 48 16
|
|
45 01 vpermps zmm0, zmm0, ZMMWORD PTR matrix$[rbp]
|
|
0006d b8 40 00 00 00 mov eax, 64 ; 00000040H
|
|
00072 48 6b c0 00 imul rax, rax, 0
|
|
00076 49 8b 8d 38 02
|
|
00 00 mov rcx, QWORD PTR ans$[r13]
|
|
0007d 62 f1 7c 48 11
|
|
04 01 vmovups ZMMWORD PTR [rcx+rax], zmm0
|
|
|
|
; 98 : }
|
|
|
|
00084 49 8d a5 10 02
|
|
00 00 lea rsp, QWORD PTR [r13+528]
|
|
0008b 5f pop rdi
|
|
0008c 5d pop rbp
|
|
0008d 41 5d pop r13
|
|
0008f c3 ret 0
|
|
float_kernel_transpose_512 ENDP
|
|
_TEXT ENDS
|
|
; Function compile flags: /Odtp /RTCsu /ZI
|
|
; File D:\platform-dev\StgSharp.Native\sn-src\m.basic.x86.c
|
|
; COMDAT float_kernel_transpose_avx
|
|
_TEXT SEGMENT
|
|
col_low$ = 32
|
|
col_high$ = 96
|
|
unpack_low$ = 160
|
|
unpack_high$ = 224
|
|
right$ = 528
|
|
ans$ = 536
|
|
float_kernel_transpose_avx PROC ; COMDAT
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|
|
|
; 76 : {
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|
|
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$LN3:
|
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00000 48 89 54 24 10 mov QWORD PTR [rsp+16], rdx
|
|
00005 48 89 4c 24 08 mov QWORD PTR [rsp+8], rcx
|
|
0000a 41 55 push r13
|
|
0000c 55 push rbp
|
|
0000d 57 push rdi
|
|
0000e 48 81 ec 10 02
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|
00 00 sub rsp, 528 ; 00000210H
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|
00015 4c 8d 6c 24 20 lea r13, QWORD PTR [rsp+32]
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|
0001a 48 8d 6c 24 40 lea rbp, QWORD PTR [rsp+64]
|
|
0001f 48 83 e5 e0 and rbp, -32 ; ffffffffffffffe0H
|
|
00023 48 8d 0d 00 00
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|
00 00 lea rcx, OFFSET FLAT:__E2B4C3B7_m@basic@x86@c
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0002a e8 00 00 00 00 call __CheckForDebuggerJustMyCode
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0002f 90 npad 1
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|
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; 77 : register __m256 col_low = right->f32_y[0];
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00030 b8 20 00 00 00 mov eax, 32 ; 00000020H
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00035 48 6b c0 00 imul rax, rax, 0
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00039 49 8b 8d 10 02
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|
00 00 mov rcx, QWORD PTR right$[r13]
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|
00040 c5 fc 10 04 01 vmovups ymm0, YMMWORD PTR [rcx+rax]
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00045 c5 fc 11 45 20 vmovups YMMWORD PTR col_low$[rbp], ymm0
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; 78 : register __m256 col_high = right->f32_y[1];
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0004a b8 20 00 00 00 mov eax, 32 ; 00000020H
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0004f 48 6b c0 01 imul rax, rax, 1
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|
00053 49 8b 8d 10 02
|
|
00 00 mov rcx, QWORD PTR right$[r13]
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|
0005a c5 fc 10 04 01 vmovups ymm0, YMMWORD PTR [rcx+rax]
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|
0005f c5 fc 11 45 60 vmovups YMMWORD PTR col_high$[rbp], ymm0
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|
|
|
; 79 :
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|
; 80 : register __m256 unpack_low = _mm256_unpacklo_ps(col_low, col_high);
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|
|
|
00064 c5 fc 10 45 20 vmovups ymm0, YMMWORD PTR col_low$[rbp]
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|
00069 c5 fc 14 45 60 vunpcklps ymm0, ymm0, YMMWORD PTR col_high$[rbp]
|
|
0006e c5 fc 11 85 a0
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00 00 00 vmovups YMMWORD PTR unpack_low$[rbp], ymm0
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|
|
|
; 81 : register __m256 unpack_high = _mm256_unpackhi_ps(col_low, col_high);
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|
|
|
00076 c5 fc 10 45 20 vmovups ymm0, YMMWORD PTR col_low$[rbp]
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|
0007b c5 fc 15 45 60 vunpckhps ymm0, ymm0, YMMWORD PTR col_high$[rbp]
|
|
00080 c5 fc 11 85 e0
|
|
00 00 00 vmovups YMMWORD PTR unpack_high$[rbp], ymm0
|
|
|
|
; 82 :
|
|
; 83 : col_low = _mm256_permute2f128_ps(unpack_low, unpack_high, 0x20);
|
|
|
|
00088 c5 fc 10 85 a0
|
|
00 00 00 vmovups ymm0, YMMWORD PTR unpack_low$[rbp]
|
|
00090 c4 e3 7d 06 85
|
|
e0 00 00 00 20 vperm2f128 ymm0, ymm0, YMMWORD PTR unpack_high$[rbp], 32 ; 00000020H
|
|
0009a c5 fc 11 45 20 vmovups YMMWORD PTR col_low$[rbp], ymm0
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|
|
|
; 84 : col_high = _mm256_permute2f128_ps(unpack_low, unpack_high, 0x31);
|
|
|
|
0009f c5 fc 10 85 a0
|
|
00 00 00 vmovups ymm0, YMMWORD PTR unpack_low$[rbp]
|
|
000a7 c4 e3 7d 06 85
|
|
e0 00 00 00 31 vperm2f128 ymm0, ymm0, YMMWORD PTR unpack_high$[rbp], 49 ; 00000031H
|
|
000b1 c5 fc 11 45 60 vmovups YMMWORD PTR col_high$[rbp], ymm0
|
|
|
|
; 85 :
|
|
; 86 : ans->f32_y[0] = _mm256_shuffle_ps(col_high, col_low, _MM_SHUFFLE(2, 0, 2, 0));
|
|
|
|
000b6 c5 fc 10 45 60 vmovups ymm0, YMMWORD PTR col_high$[rbp]
|
|
000bb c5 fc c6 45 20
|
|
88 vshufps ymm0, ymm0, YMMWORD PTR col_low$[rbp], 136 ; 00000088H
|
|
000c1 b8 20 00 00 00 mov eax, 32 ; 00000020H
|
|
000c6 48 6b c0 00 imul rax, rax, 0
|
|
000ca 49 8b 8d 18 02
|
|
00 00 mov rcx, QWORD PTR ans$[r13]
|
|
000d1 c5 fc 11 04 01 vmovups YMMWORD PTR [rcx+rax], ymm0
|
|
|
|
; 87 : ans->f32_y[1] = _mm256_shuffle_ps(col_high, col_low, _MM_SHUFFLE(3, 1, 3, 1));
|
|
|
|
000d6 c5 fc 10 45 60 vmovups ymm0, YMMWORD PTR col_high$[rbp]
|
|
000db c5 fc c6 45 20
|
|
dd vshufps ymm0, ymm0, YMMWORD PTR col_low$[rbp], 221 ; 000000ddH
|
|
000e1 b8 20 00 00 00 mov eax, 32 ; 00000020H
|
|
000e6 48 6b c0 01 imul rax, rax, 1
|
|
000ea 49 8b 8d 18 02
|
|
00 00 mov rcx, QWORD PTR ans$[r13]
|
|
000f1 c5 fc 11 04 01 vmovups YMMWORD PTR [rcx+rax], ymm0
|
|
|
|
; 88 : }
|
|
|
|
000f6 49 8d a5 f0 01
|
|
00 00 lea rsp, QWORD PTR [r13+496]
|
|
000fd 5f pop rdi
|
|
000fe 5d pop rbp
|
|
000ff 41 5d pop r13
|
|
00101 c3 ret 0
|
|
float_kernel_transpose_avx ENDP
|
|
_TEXT ENDS
|
|
; Function compile flags: /Odtp /RTCsu /ZI
|
|
; File D:\platform-dev\StgSharp.Native\sn-src\m.basic.x86.c
|
|
; COMDAT float_kernel_transpose_sse
|
|
_TEXT SEGMENT
|
|
col0$ = 16
|
|
col1$ = 64
|
|
col2$ = 112
|
|
col3$ = 160
|
|
tmp0$ = 208
|
|
tmp1$ = 256
|
|
tmp2$ = 304
|
|
tmp3$ = 352
|
|
right$ = 608
|
|
ans$ = 616
|
|
float_kernel_transpose_sse PROC ; COMDAT
|
|
|
|
; 59 : {
|
|
|
|
$LN3:
|
|
00000 48 89 54 24 10 mov QWORD PTR [rsp+16], rdx
|
|
00005 48 89 4c 24 08 mov QWORD PTR [rsp+8], rcx
|
|
0000a 55 push rbp
|
|
0000b 57 push rdi
|
|
0000c 48 81 ec 68 02
|
|
00 00 sub rsp, 616 ; 00000268H
|
|
00013 48 8d 6c 24 20 lea rbp, QWORD PTR [rsp+32]
|
|
00018 48 8d 0d 00 00
|
|
00 00 lea rcx, OFFSET FLAT:__E2B4C3B7_m@basic@x86@c
|
|
0001f e8 00 00 00 00 call __CheckForDebuggerJustMyCode
|
|
00024 90 npad 1
|
|
|
|
; 60 : register __m128 col0 = right->f32_x[0];
|
|
|
|
00025 b8 10 00 00 00 mov eax, 16
|
|
0002a 48 6b c0 00 imul rax, rax, 0
|
|
0002e 48 8b 8d 60 02
|
|
00 00 mov rcx, QWORD PTR right$[rbp]
|
|
00035 0f 10 04 01 movups xmm0, XMMWORD PTR [rcx+rax]
|
|
00039 0f 11 45 10 movups XMMWORD PTR col0$[rbp], xmm0
|
|
|
|
; 61 : register __m128 col1 = right->f32_x[1];
|
|
|
|
0003d b8 10 00 00 00 mov eax, 16
|
|
00042 48 6b c0 01 imul rax, rax, 1
|
|
00046 48 8b 8d 60 02
|
|
00 00 mov rcx, QWORD PTR right$[rbp]
|
|
0004d 0f 10 04 01 movups xmm0, XMMWORD PTR [rcx+rax]
|
|
00051 0f 11 45 40 movups XMMWORD PTR col1$[rbp], xmm0
|
|
|
|
; 62 : register __m128 col2 = right->f32_x[2];
|
|
|
|
00055 b8 10 00 00 00 mov eax, 16
|
|
0005a 48 6b c0 02 imul rax, rax, 2
|
|
0005e 48 8b 8d 60 02
|
|
00 00 mov rcx, QWORD PTR right$[rbp]
|
|
00065 0f 10 04 01 movups xmm0, XMMWORD PTR [rcx+rax]
|
|
00069 0f 11 45 70 movups XMMWORD PTR col2$[rbp], xmm0
|
|
|
|
; 63 : register __m128 col3 = right->f32_x[3];
|
|
|
|
0006d b8 10 00 00 00 mov eax, 16
|
|
00072 48 6b c0 03 imul rax, rax, 3
|
|
00076 48 8b 8d 60 02
|
|
00 00 mov rcx, QWORD PTR right$[rbp]
|
|
0007d 0f 10 04 01 movups xmm0, XMMWORD PTR [rcx+rax]
|
|
00081 0f 11 85 a0 00
|
|
00 00 movups XMMWORD PTR col3$[rbp], xmm0
|
|
|
|
; 64 : register __m128 tmp0 = _mm_unpacklo_ps(col0, col1);
|
|
|
|
00088 0f 28 45 10 movaps xmm0, XMMWORD PTR col0$[rbp]
|
|
0008c 0f 14 45 40 unpcklps xmm0, XMMWORD PTR col1$[rbp]
|
|
00090 0f 29 85 d0 00
|
|
00 00 movaps XMMWORD PTR tmp0$[rbp], xmm0
|
|
|
|
; 65 : register __m128 tmp1 = _mm_unpackhi_ps(col0, col1);
|
|
|
|
00097 0f 28 45 10 movaps xmm0, XMMWORD PTR col0$[rbp]
|
|
0009b 0f 15 45 40 unpckhps xmm0, XMMWORD PTR col1$[rbp]
|
|
0009f 0f 29 85 00 01
|
|
00 00 movaps XMMWORD PTR tmp1$[rbp], xmm0
|
|
|
|
; 66 : register __m128 tmp2 = _mm_unpacklo_ps(col2, col3);
|
|
|
|
000a6 0f 28 45 70 movaps xmm0, XMMWORD PTR col2$[rbp]
|
|
000aa 0f 14 85 a0 00
|
|
00 00 unpcklps xmm0, XMMWORD PTR col3$[rbp]
|
|
000b1 0f 29 85 30 01
|
|
00 00 movaps XMMWORD PTR tmp2$[rbp], xmm0
|
|
|
|
; 67 : register __m128 tmp3 = _mm_unpackhi_ps(col2, col3);
|
|
|
|
000b8 0f 28 45 70 movaps xmm0, XMMWORD PTR col2$[rbp]
|
|
000bc 0f 15 85 a0 00
|
|
00 00 unpckhps xmm0, XMMWORD PTR col3$[rbp]
|
|
000c3 0f 29 85 60 01
|
|
00 00 movaps XMMWORD PTR tmp3$[rbp], xmm0
|
|
|
|
; 68 :
|
|
; 69 : ans->f32_x[0] = _mm_movelh_ps(tmp0, tmp2);
|
|
|
|
000ca 0f 28 85 d0 00
|
|
00 00 movaps xmm0, XMMWORD PTR tmp0$[rbp]
|
|
000d1 0f 28 8d 30 01
|
|
00 00 movaps xmm1, XMMWORD PTR tmp2$[rbp]
|
|
000d8 0f 16 c1 movlhps xmm0, xmm1
|
|
000db b8 10 00 00 00 mov eax, 16
|
|
000e0 48 6b c0 00 imul rax, rax, 0
|
|
000e4 48 8b 8d 68 02
|
|
00 00 mov rcx, QWORD PTR ans$[rbp]
|
|
000eb 0f 11 04 01 movups XMMWORD PTR [rcx+rax], xmm0
|
|
|
|
; 70 : ans->f32_x[1] = _mm_movehl_ps(tmp2, tmp0);
|
|
|
|
000ef 0f 28 85 d0 00
|
|
00 00 movaps xmm0, XMMWORD PTR tmp0$[rbp]
|
|
000f6 0f 28 8d 30 01
|
|
00 00 movaps xmm1, XMMWORD PTR tmp2$[rbp]
|
|
000fd 0f 12 c8 movhlps xmm1, xmm0
|
|
00100 0f 28 c1 movaps xmm0, xmm1
|
|
00103 b8 10 00 00 00 mov eax, 16
|
|
00108 48 6b c0 01 imul rax, rax, 1
|
|
0010c 48 8b 8d 68 02
|
|
00 00 mov rcx, QWORD PTR ans$[rbp]
|
|
00113 0f 11 04 01 movups XMMWORD PTR [rcx+rax], xmm0
|
|
|
|
; 71 : ans->f32_x[2] = _mm_movelh_ps(tmp1, tmp3);
|
|
|
|
00117 0f 28 85 00 01
|
|
00 00 movaps xmm0, XMMWORD PTR tmp1$[rbp]
|
|
0011e 0f 28 8d 60 01
|
|
00 00 movaps xmm1, XMMWORD PTR tmp3$[rbp]
|
|
00125 0f 16 c1 movlhps xmm0, xmm1
|
|
00128 b8 10 00 00 00 mov eax, 16
|
|
0012d 48 6b c0 02 imul rax, rax, 2
|
|
00131 48 8b 8d 68 02
|
|
00 00 mov rcx, QWORD PTR ans$[rbp]
|
|
00138 0f 11 04 01 movups XMMWORD PTR [rcx+rax], xmm0
|
|
|
|
; 72 : ans->f32_x[3] = _mm_movehl_ps(tmp3, tmp1);
|
|
|
|
0013c 0f 28 85 00 01
|
|
00 00 movaps xmm0, XMMWORD PTR tmp1$[rbp]
|
|
00143 0f 28 8d 60 01
|
|
00 00 movaps xmm1, XMMWORD PTR tmp3$[rbp]
|
|
0014a 0f 12 c8 movhlps xmm1, xmm0
|
|
0014d 0f 28 c1 movaps xmm0, xmm1
|
|
00150 b8 10 00 00 00 mov eax, 16
|
|
00155 48 6b c0 03 imul rax, rax, 3
|
|
00159 48 8b 8d 68 02
|
|
00 00 mov rcx, QWORD PTR ans$[rbp]
|
|
00160 0f 11 04 01 movups XMMWORD PTR [rcx+rax], xmm0
|
|
|
|
; 73 : }
|
|
|
|
00164 48 8d a5 48 02
|
|
00 00 lea rsp, QWORD PTR [rbp+584]
|
|
0016b 5f pop rdi
|
|
0016c 5d pop rbp
|
|
0016d c3 ret 0
|
|
float_kernel_transpose_sse ENDP
|
|
_TEXT ENDS
|
|
END
|