before merge

This commit is contained in:
Nitload
2026-05-04 17:22:29 +08:00
parent 1338bf2801
commit e1167bb071
+8 -22
View File
@@ -2,8 +2,8 @@
// -----------------------------------------------------------------------
// file="L4"
// Project: StgSharp
// AuthorGroup: Nitload
// Copyright (c) Nitload. All rights reserved.
// AuthorGroup: Nitload Space
// Copyright (c) Nitload Space. All rights reserved.
//
// Permission is hereby granted, free of charge, to any person obtaining a copy
// of this software and associated documentation files (the "Software"), to deal
@@ -43,7 +43,6 @@ namespace StgSharp.HighPerformance.Memory
private const int PredictionCount = 2048;
private const int PredictionLeastAhead = 1024;
private static readonly IIntrinsicKernel _intrinsic = IIntrinsicKernel.Instance;
private readonly CacheLineHead* _head;
private readonly MapArray* _mapCount;
private readonly PredictionArray* _predictCount;
@@ -62,12 +61,7 @@ namespace StgSharp.HighPerformance.Memory
private readonly Slab _entryManager;
private readonly SwissTable _map;
public L4(
int bindedNuma,
nuint bufferSize = 8192 * 8192,
int align = 16,
nuint maxCacheLineSize = 8192
)
public L4(int bindedNuma, nuint bufferSize = 8192 * 8192, int align = 16, nuint maxCacheLineSize = 8192)
{
_bindedNuma = bindedNuma;
@@ -90,8 +84,8 @@ namespace StgSharp.HighPerformance.Memory
// init all components with the buffer, and move the buffer pointer forward.
nuint _buffer = _baseAddress + normalizedBufferSize;
_entryManager = new Slab(_buffer);
_bufferAllocator = new HLSF(entrySize, align, maxCacheLineSize, (void*)_baseAddress,
static _ => { }, _entryManager);
_bufferAllocator = new HLSF(entrySize, align, maxCacheLineSize, (void*)_baseAddress, static _ => { },
_entryManager);
ptr += entrySize;
_head = (CacheLineHead*)ptr;
ptr += headSize;
@@ -117,9 +111,7 @@ namespace StgSharp.HighPerformance.Memory
// public IL4Predict PrefetchPredict { get; set; }
[MethodImpl(MethodImplOptions.AggressiveInlining)]
public void ContinueOnce(
L4CacheLine line
)
public void ContinueOnce(L4CacheLine line)
{
if (line.Address > 0) {
_ = Interlocked.Decrement(ref _aheadCount);
@@ -157,9 +149,7 @@ namespace StgSharp.HighPerformance.Memory
}
[MethodImpl(MethodImplOptions.AggressiveInlining)]
public L4CacheLine Map(
ref CacheLineDescription prediction
)
public L4CacheLine Map(ref CacheLineDescription prediction)
{
if ((_aheadCount < PredictionLeastAhead) && !_exhausted)
{
@@ -212,11 +202,7 @@ namespace StgSharp.HighPerformance.Memory
private ref int _refCount;
private nuint _handle;
internal L4CacheLine(
nuint handle,
ref int activeCount,
ref int cacheRefCount
)
internal L4CacheLine(nuint handle, ref int activeCount, ref int cacheRefCount)
{
_handle = handle;
_refCount = ref cacheRefCount;