215 lines
8.3 KiB
C
215 lines
8.3 KiB
C
#include "sn_target.h"
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#if SN_IS_ARCH(SN_ARCH_X86_64)
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#include "StgSharpNative.h"
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#include "sn_intrinsic.h"
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#include "sn_intrinsic.context.x86.h"
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/* -----------------------------------------------------------------------
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* Field extraction helpers.
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*
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* SIMDID layout (64 bits, little-endian byte order in make_byte[]):
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* [3..0] Root ISA make_byte[0] low nibble
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* [7..4] Manufacture make_byte[0] high nibble
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* [15..8] MainLevel make_byte[1]
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* [31..16] AVX512 Feature make_byte[2..3] (16 bits)
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* [39..32] AMX Feature make_byte[4]
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* [47..40] AVX Feature make_byte[5]
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* [55..48] AVX10 Feature make_byte[6]
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* [63..56] uArchHi make_byte[7]
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* ----------------------------------------------------------------------- */
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#define FIELD_MAIN(id) ((unsigned char)(id).make_byte[1])
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#define FIELD_AVX512(id) \
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((uint16_t)((unsigned char)(id).make_byte[2] | ((unsigned char)(id).make_byte[3] << 8)))
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#define FIELD_AMX(id) ((unsigned char)(id).make_byte[4])
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#define FIELD_AVX(id) ((unsigned char)(id).make_byte[5])
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#define FIELD_AVX10(id) ((unsigned char)(id).make_byte[6])
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#define FIELD_UARCH(id) ((unsigned char)(id).make_byte[7])
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/* Portable popcount for a 16-bit value. */
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static int popcount16(uint16_t v)
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{
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int c = 0;
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while (v) {
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v &= v - 1;
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c++;
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}
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return c;
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}
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/* Map AVX512_IMPL 2-bit field to a strength ordinal for tie-breaking.
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* Index = impl value (0=UNKNOWN, 1=DUAL, 2=NATIVE, 3=reserved).
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* Strength: DUAL(0) < UNKNOWN(1) < NATIVE(2). */
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static const int impl_strength_table[4] = { 1, 0, 2, 1 };
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static int impl_strength(uint16_t avx512)
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{
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unsigned impl = (avx512 >> SIMDID_AVX512_IMPL_SHIFT) & 0x3u;
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return impl_strength_table[impl];
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}
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/* -----------------------------------------------------------------------
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* sn_get_unite_simd
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*
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* Produce the conservative intersection of two SIMDIDs — the strongest
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* capability set that is safe to use on BOTH cores:
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* - MainLevel : min (only assume what both cores support)
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* - AVX512 features : bitwise AND (IMPL field: pick the weaker one)
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* - AMX features : bitwise AND
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* - AVX features : bitwise AND
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* - AVX10 features : bitwise AND
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* - Root / Manu : keep left (must be same arch in practice)
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* - uArchHi : bitwise OR (HYBRID_P/E union; SIMD_DUAL set if either core is dual)
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* ----------------------------------------------------------------------- */
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SN_API SIMDID SN_DECL sn_get_unite_simd(SIMDID left, SIMDID right)
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{
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SIMDID out;
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out.mask = 0;
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/* Root + Manufacture (byte 0): prefer left (same arch assumed) */
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unsigned char lb0 = (unsigned char)left.make_byte[0];
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unsigned char rb0 = (unsigned char)right.make_byte[0];
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out.make_byte[0] = (char)(lb0 ? lb0 : rb0);
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/* MainLevel (byte 1): min */
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unsigned char lm = FIELD_MAIN(left);
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unsigned char rm = FIELD_MAIN(right);
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out.make_byte[1] = (char)(lm < rm ? lm : rm);
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/* AVX512 features (bytes 2-3): AND all bits, then fix IMPL to weaker */
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uint16_t l512 = FIELD_AVX512(left);
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uint16_t r512 = FIELD_AVX512(right);
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uint16_t merged = l512 & r512;
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/* Clear the IMPL field, then set the weaker one */
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int ls = impl_strength(l512);
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int rs = impl_strength(r512);
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int s = (ls <= rs) ? l512 : r512; /* pick the one with weaker strength ordinal */
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unsigned weak_impl = (s >> SIMDID_AVX512_IMPL_SHIFT) & 0x3u;
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merged &= ~(uint16_t)SIMDID_AVX512_IMPL_MASK;
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merged |= (uint16_t)(weak_impl << SIMDID_AVX512_IMPL_SHIFT);
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out.make_byte[2] = (char)(merged & 0xFF);
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out.make_byte[3] = (char)((merged >> 8) & 0xFF);
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/* AMX (byte 4): AND */
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out.make_byte[4] = left.make_byte[4] & right.make_byte[4];
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/* AVX (byte 5): AND */
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out.make_byte[5] = left.make_byte[5] & right.make_byte[5];
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/* AVX10 (byte 6): AND */
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out.make_byte[6] = left.make_byte[6] & right.make_byte[6];
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/* uArchHi (byte 7):
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* topology bits [1..0]: AND — conservative intersection (weaker topology wins)
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* SIMD_DUAL bit [2]: OR — dual if either core is dual */
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unsigned char lu = FIELD_UARCH(left);
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unsigned char ru = FIELD_UARCH(right);
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unsigned char topo = (lu & 0x3u) & (ru & 0x3u);
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unsigned char dual = (lu | ru) & (unsigned char)SIMDID_UARCH_SIMD_DUAL;
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out.make_byte[7] = (char)(topo | dual);
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return out;
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}
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/* -----------------------------------------------------------------------
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* sn_compare_simd
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*
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* Compare two SIMDIDs by ISA strength. Returns:
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* +1 if left is strictly stronger than right
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* -1 if left is strictly weaker than right
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* 0 if equal
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*
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* Comparison priority (most significant first):
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*
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* 1. MainLevel ([15..8])
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* Higher value = stronger. This is the primary discriminator:
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* NONE < SSE < AVX2 < AVX512 < AMX < AVX10
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*
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* 2. AVX10 vector width ([55..48])
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* Only meaningful when both MainLevel == AVX10.
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* 512W > 256W-only. Compared by the full AVX10 byte value since
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* width bits are in higher positions than version bits.
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*
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* 3. AVX512 BASE bit (bit 4 of [31..16])
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* Only meaningful when both MainLevel >= AVX512.
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* BASE=1 (F+CD+VL+DQ+BW all present) > BASE=0.
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*
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* 4. AVX512 extension popcount
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* Count of set extension bits (VNNI/BF16/FP16/VBMI/VBMI2/AI_RESERVED).
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* The IMPL and BASE bits are masked out before counting so they don't
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* inflate the extension count.
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*
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* 5. AVX512 IMPL strength (tie-break, performance hint)
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* DUAL(weakest) < UNKNOWN < NATIVE(strongest).
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* This is not ISA capability but execution-width risk.
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*
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* 6. uArchHi topology bits [1..0]
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* Numeric value: unified(11=3) > P-core(10=2) > E-core(01=1) > unknown(00=0).
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* Higher value = stronger / higher-capability core form.
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*
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* 7. uArchHi SIMD_DUAL (final tie-break)
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* Non-dual (SIMD_DUAL=0) > dual (SIMD_DUAL=1).
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* ----------------------------------------------------------------------- */
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SN_API int SN_DECL sn_compare_simd(SIMDID left, SIMDID right)
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{
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/* 1. MainLevel */
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unsigned lm = FIELD_MAIN(left);
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unsigned rm = FIELD_MAIN(right);
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if (lm != rm)
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return lm > rm ? 1 : -1;
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/* 2. AVX10 width (only when MainLevel == AVX10) */
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if (lm >= SIMDID_MAIN_LVL_AVX10) {
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unsigned la = FIELD_AVX10(left);
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unsigned ra = FIELD_AVX10(right);
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if (la != ra)
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return la > ra ? 1 : -1;
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}
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/* 3. AVX512 BASE (only when MainLevel >= AVX512) */
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if (lm >= SIMDID_MAIN_LVL_AVX512) {
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uint16_t l512 = FIELD_AVX512(left);
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uint16_t r512 = FIELD_AVX512(right);
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int lb = (l512 & SIMDID_AVX512_BASE) != 0;
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int rb = (r512 & SIMDID_AVX512_BASE) != 0;
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if (lb != rb)
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return lb > rb ? 1 : -1;
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// 4. Extension popcount (mask out BASE + IMPL + reserved low nibble)
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int drop = ~(SIMDID_AVX512_BASE | SIMDID_AVX512_IMPL_MASK | 0x000Fu);
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uint16_t ext_mask = drop & (l512 | r512); /* only consider bits set in either */
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int lp = popcount16(l512 & ext_mask);
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int rp = popcount16(r512 & ext_mask);
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if (lp != rp)
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return lp > rp ? 1 : -1;
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/* 5. IMPL strength */
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int ls = impl_strength(l512);
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int rs = impl_strength(r512);
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if (ls != rs)
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return ls > rs ? 1 : -1;
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}
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/* 6. uArchHi topology bits [1..0]: unified(3) > P(2) > E(1) > unknown(0) */
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unsigned lu = FIELD_UARCH(left);
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unsigned ru = FIELD_UARCH(right);
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unsigned lt = lu & 0x3u;
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unsigned rt = ru & 0x3u;
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if (lt != rt)
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return lt > rt ? 1 : -1;
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/* 7. uArchHi SIMD_DUAL: non-dual (SIMD_DUAL=0) > dual (SIMD_DUAL=1) */
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int ld = (lu & SIMDID_UARCH_SIMD_DUAL) != 0;
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int rd = (ru & SIMDID_UARCH_SIMD_DUAL) != 0;
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if (ld != rd)
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return ld ? -1 : 1; /* non-dual is stronger */
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return 0;
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}
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#endif
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