84 lines
3.8 KiB
C
84 lines
3.8 KiB
C
#ifndef SN_MATKERNEL
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#define SN_MATKERNEL
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#define ELEMENTSIZE(T) sizeof(T)
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#define XMMCOUNT(T) sizeof(T)
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#define YMMCOUNT(T) sizeof(T) / 2
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#define ZMMCOUNT(T) sizeof(T) / 4
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#include <immintrin.h>
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#define MAT_KERNEL(T) \
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union { \
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__m128 xmm[XMMCOUNT(T) / 4]; \
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__m256 ymm[YMMCOUNT(T) / 4]; \
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__m512 zmm[ZMMCOUNT(T) / 4]; \
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T m[4][4]; \
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}
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#define VEC(T) \
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union { \
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__m128 xmm[XMMCOUNT(T) / 4]; \
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__m256 ymm[YMMCOUNT(T) / 4]; \
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__m512 zmm[ZMMCOUNT(T) / 4]; \
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T v[4]; \
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}
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#endif
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/* Helpers (all compile-time): */
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#define SN_LANES(T_VEC, T) (sizeof(T_VEC) / sizeof(T))
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#define SN_MAX(a, b) (((a)) > ((b)) ? (a) : (b))
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#define SN_CEIL_DIV(a, b) (((a) + (b) - 1) / (b))
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/* Panel geometry helpers (all compile-time): */
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#define PANEL_Q(T, T_VEC, MINQ) SN_MAX(SN_LANES(T_VEC, T), (MINQ))
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#define PANEL_CHUNKS(T, T_VEC, MINQ) SN_CEIL_DIV(PANEL_Q(T, T_VEC, MINQ), SN_LANES(T_VEC, T))
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/*
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Column-major square panel with minimum side Q:
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- Let R = lanes per vector = sizeof(T_VEC)/sizeof(T).
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- Side length Q = max(R, MINQ) to enforce the requested minimum extent.
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- Each column is stored contiguously via CH = ceil(Q/R) vector chunks.
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- Memory layout:
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vec[col][chunk] is a T_VEC holding up to R scalars of column 'col'
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spanning rows chunk*R .. chunk*R + (R - 1).
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flat[] mirrors the same column-major order (column stride = Q).
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- SIMD view remains integer-typed; cast inside micro-kernels to the
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appropriate floating-point/integer vector type on demand.
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*/
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#define MAT_PANEL_SQ_MIN(T, T_VEC, MINQ) \
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SN_ALIGNAS(sizeof(T_VEC)) union { \
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T_VEC vec[PANEL_Q(T, T_VEC, MINQ)][PANEL_CHUNKS(T, T_VEC, MINQ)]; \
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T flat[PANEL_Q(T, T_VEC, MINQ) * PANEL_Q(T, T_VEC, MINQ)]; \
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}
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/* ISA presets with minimum square side:
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- SSE : MINQ=4 (avoid 2x2 for double)
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- AVX2 : MINQ=8
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- AVX-512: MINQ=8 (16 for float/i32 naturally, so this is a no-op there)
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*/
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/* SSE panel layout: column-major buffer holding 4 logical columns with MINQ=4.
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Columns: each column packs up to four scalars so ALIGN equals sizeof(__m128).
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Alignment: every column boundary lands on a 16-byte multiple for XMM loads. */
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#define MAT_PANEL_SSE(T) MAT_PANEL_SQ_MIN(T, __m128, 4)
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/* AVX2 panel layout: column-major buffer holding 8 logical columns with MINQ=8.
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Columns: each column stores eight elements via two 256-bit chunks when T is 32-bit.
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Alignment: column starts are 32-byte aligned so AVX2 loads/stores remain contiguous. */
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#define MAT_PANEL_AVX(T) MAT_PANEL_SQ_MIN(T, __m256, 8)
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/* AVX-512 panel layout: column-major buffer holding 8 or more columns depending on T.
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Columns: each column expands to ceil(Q/lanes) ZMM chunks; default MINQ=8 keeps double-wide tiles.
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Alignment: column starts sit on 64-byte boundaries to match AVX-512 streaming access. */
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#define MAT_PANEL_512(T) MAT_PANEL_SQ_MIN(T, __m512, 8)
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/* Access helpers (all compile-time friendly):
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Given Q = PANEL_Q(...), CH = PANEL_CHUNKS(...), R = lanes per vector:
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- Column c occupies vec[c][0..CH-1].
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- Row r inside column c is located at vec[c][r / R] with lane (r % R).
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*/
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#define PANEL_COL_VEC(panel_obj, c, chunk) ((panel_obj).vec[(int)(c)][(int)(chunk)])
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/* Scalar flat index helper for column-major addressing */
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#define PANEL_ELEM(panel_obj, T, T_VEC, MINQ, r, c) \
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((panel_obj).flat[(int)(c) * PANEL_Q(T, T_VEC, MINQ) + (int)(r)])
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