357 lines
13 KiB
C
357 lines
13 KiB
C
#include "sn_target.h"
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/* clang-format off */
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#if SN_IS_ARCH(SN_ARCH_X86_64)
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#include "sn_intrinsic.h"
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#include "StgSharpNative.h"
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static SIMDID global_simdid = { 0 };
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#include "sn_intrinsic.context.x86.h"
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#include <immintrin.h>
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#include <string.h>
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#if defined(_MSC_VER)
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#include <intrin.h>
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#else
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#include <cpuid.h>
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#endif
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static void get_cpuid(int leaf, int subleaf, int *eax, int *ebx, int *ecx, int *edx)
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{
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#if defined(_MSC_VER)
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int regs[4];
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__cpuidex(regs, leaf, subleaf);
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*eax = regs[0];
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*ebx = regs[1];
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*ecx = regs[2];
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*edx = regs[3];
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#else
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unsigned int a, b, c, d;
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__cpuid_count((unsigned int)leaf, (unsigned int)subleaf, a, b, c, d);
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*eax = (int)a;
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*ebx = (int)b;
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*ecx = (int)c;
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*edx = (int)d;
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#endif
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}
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static int xgetbv_has_xmm_ymm(void)
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{
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#if defined(_MSC_VER)
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unsigned __int64 xcr0 = _xgetbv(0);
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#else
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unsigned long long xcr0 = __builtin_ia32_xgetbv(0);
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#endif
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return ((xcr0 & 0x6) == 0x6);
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}
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static int xgetbv_has_avx512_state(void)
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{
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const unsigned long long mask = (1ull << 0) | (1ull << 1) | (1ull << 2) | (1ull << 5) |
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(1ull << 6);
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#if defined(_MSC_VER)
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unsigned __int64 xcr0 = _xgetbv(0);
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#else
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unsigned long long xcr0 = __builtin_ia32_xgetbv(0);
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#endif
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return ((xcr0 & mask) == mask);
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}
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static void decode_family_model(int cpuid1_eax, int *family, int *model)
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{
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int family_value = 0;
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int model_value = 0;
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const int base_fam = (cpuid1_eax >> 8) & 0xF;
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const int ext_fam = (cpuid1_eax >> 20) & 0xFF;
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const int base_model = (cpuid1_eax >> 4) & 0xF;
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const int ext_model = (cpuid1_eax >> 16) & 0xF;
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if (base_fam == 0xF) {
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family_value = base_fam + ext_fam;
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} else {
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family_value = base_fam;
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}
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if ((base_fam == 0x6) || (base_fam == 0xF)) {
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model_value = (ext_model << 4) | base_model;
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} else {
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model_value = base_model;
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}
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*family = family_value;
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*model = model_value;
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}
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/* AVX-512 execution-width classification for AMD, by CPU family.
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* Zen4 (0x19): single 256-bit ALU, 512-bit op = two 256-bit micro-ops (dual-pump) → DUAL.
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* Zen5+ (>=0x1A): native 512-bit execution units → NATIVE.
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* Other/future AMD families → UNKNOWN (conservative). */
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static uint64_t amd_avx512_impl(int family)
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{
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if (family == 0x19) {
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return SIMDID_AVX512_IMPL_DUAL;
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} else if (family >= 0x1A) {
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return SIMDID_AVX512_IMPL_NATIVE;
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} else {
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return SIMDID_AVX512_IMPL_UNKNOWN;
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}
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}
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/* Returns 1 if this AMD/Hygon CPU uses split-lane YMM (two fused 128-bit execution units).
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* - AMD Zen1 (family 0x17, model < 0x30) and Zen+ (0x18-0x2F) use a split/glued path.
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* - Hygon Dhyana is architecturally Zen1-based; always split.
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* - AMD Zen2+ (family 0x17 model >= 0x30, family 0x19+) have native 256-bit execution. */
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static int is_amd_glue_ymm(const char *vendor, int cpuid1_eax)
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{
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int family = 0;
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int model = 0;
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if (strcmp(vendor, "HygonGenuine") == 0) {
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return 1;
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}
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if (strcmp(vendor, "AuthenticAMD") != 0) {
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return 0;
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}
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decode_family_model(cpuid1_eax, &family, &model);
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return (family == 0x17) && (model < 0x30);
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}
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SN_API SIMDID SN_DECL sn_get_simd_level_local()
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{
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SIMDID simdid = { 0 };
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int eax = 0;
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int ebx = 0;
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int ecx = 0;
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int edx = 0;
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int family = 0;
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int model = 0;
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get_cpuid(0, 0, &eax, &ebx, &ecx, &edx);
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const int max_basic_leaf = eax;
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char vendor[13];
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memcpy(vendor + 0, &ebx, 4);
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memcpy(vendor + 4, &edx, 4);
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memcpy(vendor + 8, &ecx, 4);
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vendor[12] = '\0';
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const int is_intel = (strcmp(vendor, "GenuineIntel") == 0);
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const int is_amd = (strcmp(vendor, "AuthenticAMD") == 0);
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const int is_hygon = (strcmp(vendor, "HygonGenuine") == 0);
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const int is_centaur = (strcmp(vendor, "CentaurHauls") == 0);
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const int is_zhaoxin = (strcmp(vendor, " Shanghai ") == 0);
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const int is_via = is_centaur || is_zhaoxin;
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get_cpuid(1, 0, &eax, &ebx, &ecx, &edx);
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const int cpuid1_eax = eax;
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decode_family_model(cpuid1_eax, &family, &model);
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(void)model;
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const int has_sse42 = (ecx & (1 << 20)) != 0;
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const int has_avx = (ecx & (1 << 28)) != 0;
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const int has_osxsave = (ecx & (1 << 27)) != 0;
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const int has_fma = (ecx & (1 << 12)) != 0;
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const int has_f16c = (ecx & (1 << 29)) != 0;
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const uint64_t root = SIMDID_PACK_ROOT(SIMDID_ROOT_X86_64);
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uint64_t manu_code = SIMDID_MANU_UNKNOWN;
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if (is_intel) {
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manu_code = SIMDID_MANU_INTEL;
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} else if (is_amd) {
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manu_code = SIMDID_MANU_AMD;
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} else if (is_hygon) {
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manu_code = SIMDID_MANU_HYGON;
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} else if (is_via) {
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manu_code = SIMDID_MANU_VIA;
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}
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const uint64_t manu = SIMDID_PACK_MANU(manu_code);
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uint64_t main_lvl = SIMDID_PACK_MAIN(SIMDID_MAIN_LVL_NONE);
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uint64_t avx_bits = 0;
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uint64_t avx512_bits = 0;
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uint64_t amx_bits = 0;
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uint64_t avx10_bits = 0;
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uint64_t uarch_bits = 0;
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int has_hybrid = 0;
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if (has_sse42) {
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main_lvl = SIMDID_PACK_MAIN(SIMDID_MAIN_LVL_SSE);
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}
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if (has_avx && has_osxsave && xgetbv_has_xmm_ymm()) {
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avx_bits |= SIMDID_AVX;
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if (is_amd_glue_ymm(vendor, cpuid1_eax) || is_via) {
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avx_bits |= SIMDID_AVX_DUAL;
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}
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if (max_basic_leaf >= 7) {
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get_cpuid(7, 0, &eax, &ebx, &ecx, &edx);
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const int has_avx2 = (ebx & (1 << 5)) != 0;
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const int has_avx512f = (ebx & (1 << 16)) != 0;
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const int has_avx512dq = (ebx & (1 << 17)) != 0;
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const int has_avx512bw = (ebx & (1 << 30)) != 0;
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const int has_avx512vl = (ebx & (1u << 31)) != 0;
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const int has_avx512_vnni = (ecx & (1 << 11)) != 0;
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const int has_vbmi = (ecx & (1 << 1)) != 0;
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const int has_vbmi2 = (ecx & (1 << 6)) != 0;
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const int has_amx_tile = (edx & (1 << 24)) != 0;
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const int has_amx_int8 = (edx & (1 << 25)) != 0;
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const int has_amx_bf16 = (edx & (1 << 22)) != 0;
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has_hybrid = (edx & (1 << 15)) != 0;
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int has_bf16 = 0;
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int has_fp16 = 0;
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int has_avx10 = 0;
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if (eax >= 1) {
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get_cpuid(7, 1, &eax, &ebx, &ecx, &edx);
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has_bf16 = (eax & (1 << 5)) != 0;
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has_fp16 = (eax & (1 << 23)) != 0;
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has_avx10 = (edx & (1 << 19)) != 0;
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}
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if (has_avx2) {
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avx_bits |= SIMDID_AVX2;
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if (has_fma) {
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avx_bits |= SIMDID_AVX_FMA;
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}
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if (has_f16c) {
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avx_bits |= SIMDID_AVX_F16C;
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}
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main_lvl = SIMDID_PACK_MAIN(SIMDID_MAIN_LVL_AVX2);
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}
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if (has_avx512f && xgetbv_has_avx512_state()) {
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if (has_avx512bw && has_avx512vl && has_avx512dq) {
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avx512_bits |= SIMDID_AVX512_BASE;
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}
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if (has_avx512_vnni) {
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avx512_bits |= SIMDID_AVX512_VNNI;
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}
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if (has_bf16) {
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avx512_bits |= SIMDID_AVX512_BF16;
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}
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if (has_fp16) {
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avx512_bits |= SIMDID_AVX512_FP16;
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}
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if (has_vbmi) {
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avx512_bits |= SIMDID_AVX512_VBMI;
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}
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if (has_vbmi2) {
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avx512_bits |= SIMDID_AVX512_VBMI2;
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}
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if (is_intel) {
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avx512_bits |= SIMDID_AVX512_IMPL_NATIVE;
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} else if (is_amd) {
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avx512_bits |= amd_avx512_impl(family);
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} else {
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avx512_bits |= SIMDID_AVX512_IMPL_UNKNOWN;
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}
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main_lvl = SIMDID_PACK_MAIN(SIMDID_MAIN_LVL_AVX512);
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if (has_amx_tile) {
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amx_bits |= SIMDID_AMX_TILE;
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if (has_amx_int8) {
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amx_bits |= SIMDID_AMX_INT8;
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}
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if (has_amx_bf16) {
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amx_bits |= SIMDID_AMX_BF16;
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}
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main_lvl = SIMDID_PACK_MAIN(SIMDID_MAIN_LVL_AMX);
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}
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if (has_avx10 && (max_basic_leaf >= 0x24)) {
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int a10_eax = 0;
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int a10_ebx = 0;
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int a10_ecx = 0;
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int a10_edx = 0;
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int avx10_ver = 0;
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int has_256w = 0;
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int has_512w = 0;
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get_cpuid(0x24, 0, &a10_eax, &a10_ebx, &a10_ecx, &a10_edx);
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avx10_ver = a10_ebx & 0xFF;
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if (avx10_ver >= 1) {
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avx10_bits |= SIMDID_AVX10 | SIMDID_AVX10_V1;
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if (avx10_ver >= 2) {
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avx10_bits |= SIMDID_AVX10_V2;
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}
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has_256w = (a10_ebx & (1 << 17)) != 0;
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has_512w = (a10_ebx & (1 << 18)) != 0;
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if (has_256w) {
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avx10_bits |= SIMDID_AVX10_256W;
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}
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if (has_512w) {
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avx10_bits |= SIMDID_AVX10_512W;
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}
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main_lvl = SIMDID_PACK_MAIN(SIMDID_MAIN_LVL_AVX10);
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}
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}
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}
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}
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}
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if (has_hybrid && (max_basic_leaf >= 0x1A)) {
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int h_eax = 0;
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int h_ebx = 0;
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int h_ecx = 0;
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int h_edx = 0;
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get_cpuid(0x1A, 0, &h_eax, &h_ebx, &h_ecx, &h_edx);
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{
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const unsigned core_type = (unsigned)(h_eax >> 24) & 0xFFU;
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if (core_type == 0x40U) {
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uarch_bits |= SIMDID_UARCH_HYBRID_P;
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} else if (core_type == 0x20U) {
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uarch_bits |= SIMDID_UARCH_HYBRID_E;
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}
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}
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} else {
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uarch_bits |= SIMDID_UARCH_HYBRID_P | SIMDID_UARCH_HYBRID_E;
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}
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{
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const int has_avx_dual = (avx_bits & SIMDID_AVX_DUAL) != 0;
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const uint64_t avx512_impl = avx512_bits & SIMDID_AVX512_IMPL_MASK;
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const int has_avx512_dual = avx512_impl == SIMDID_AVX512_IMPL_DUAL;
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if (has_avx_dual || has_avx512_dual) {
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uarch_bits |= SIMDID_UARCH_SIMD_DUAL;
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}
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}
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{
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uint64_t final_mask = root;
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final_mask |= manu;
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final_mask |= main_lvl;
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final_mask |= SIMDID_PACK_AVX512(avx512_bits);
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final_mask |= SIMDID_PACK_AMX(amx_bits);
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final_mask |= SIMDID_PACK_AVX(avx_bits);
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final_mask |= SIMDID_PACK_AVX10(avx10_bits);
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final_mask |= SIMDID_PACK_UARCH(uarch_bits);
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simdid.mask = final_mask;
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}
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return simdid;
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}
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SN_API SIMDID SN_DECL sn_get_simd_level_global()
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{
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if (global_simdid.mask) {
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return global_simdid;
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}
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global_simdid = sn_get_simd_level_local();
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return global_simdid;
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}
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#endif
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