; Listing generated by Microsoft (R) Optimizing Compiler Version 19.44.35220.0 include listing.inc INCLUDELIB MSVCRTD INCLUDELIB OLDNAMES _DATA SEGMENT COMM infolog:BYTE:0200H _DATA ENDS msvcjmc SEGMENT __5C8CA4D3_mmintrin@h DB 01H __8C83BECC_concurrencysal@h DB 01H __608E3340_sal@h DB 01H __FB67E29A_vadefs@h DB 01H __1D1B619C_vcruntime@h DB 01H __735960E1_corecrt@h DB 01H __211DB995_corecrt_malloc@h DB 01H __7CD62D9E_malloc@h DB 01H __9DCE0DC8_xmmintrin@h DB 01H __4C2AD0C7_winpackagefamily@h DB 01H __9DED9ED1_winapifamily@h DB 01H __12FEDF4E_sdkddkver@h DB 01H __9BAEE128_excpt@h DB 01H __B7B53233_stdarg@h DB 01H __6B04FCB3_specstrings_undef@h DB 01H __F4027AF7_specstrings_strict@h DB 01H __B90340D4_sdv_driverspecs@h DB 01H __BFFF5AD3_driverspecs@h DB 01H __32847078_specstrings@h DB 01H __108B2620_corecrt_wctype@h DB 01H __6CD6613D_ctype@h DB 01H __30902A1F_kernelspecs@h DB 01H __376FD5CA_basetsd@h DB 01H __13DE2371_errno@h DB 01H __8C6AE390_vcruntime_string@h DB 01H __8ACB2152_corecrt_memcpy_s@h DB 01H __EA6C9D17_corecrt_memory@h DB 01H __0DF2AF52_corecrt_wstring@h DB 01H __6E889ECC_string@h DB 01H __9BEDF4DE_guiddef@h DB 01H __51BFD2FE_pshpack4@h DB 01H __31652CEA_poppack@h DB 01H __5532AE4C_pshpack2@h DB 01H __58A52B9A_pshpack8@h DB 01H __57741015_pshpack1@h DB 01H __CDE68C90_apiset@h DB 01H __0BF06E8D_ktmtypes@h DB 01H __40C200C0_winnt@h DB 01H __9336F789_minwindef@h DB 01H __55136115_windef@h DB 01H __32205BF0_apisetcconv@h DB 01H __B48FDEA0_minwinbase@h DB 01H __3551B028_apiquery2@h DB 01H __65BE04AA_processenv@h DB 01H __4767CA46_fileapi@h DB 01H __282E6C4B_fileapifromapp@h DB 01H __393AF12C_debugapi@h DB 01H __EBC502B8_utilapiset@h DB 01H __1EAD8C69_handleapi@h DB 01H __D8EF9B29_errhandlingapi@h DB 01H __97FC1204_fibersapi@h DB 01H __27448220_namedpipeapi@h DB 01H __6EA33B2A_profileapi@h DB 01H __EAC6F673_heapapi@h DB 01H __D64EEA5A_ioapiset@h DB 01H __144BD4B6_synchapi@h DB 01H __03B1C640_interlockedapi@h DB 01H __DC64CB38_processthreadsapi@h DB 01H __D719B518_sysinfoapi@h DB 01H __410385B1_memoryapi@h DB 01H __C1AD45EF_enclaveapi@h DB 01H __F4C3AA32_threadpoollegacyapiset@h DB 01H __AC5A7A9F_threadpoolapiset@h DB 01H __F5254B21_jobapi@h DB 01H __BCEA6EE8_jobapi2@h DB 01H __D18ACE72_wow64apiset@h DB 01H __669B0D4A_libloaderapi@h DB 01H __645F7034_securitybaseapi@h DB 01H __67E58557_namespaceapi@h DB 01H __599D9D3A_systemtopologyapi@h DB 01H __2337E373_processtopologyapi@h DB 01H __02BFF239_securityappcontainer@h DB 01H __9C196272_realtimeapiset@h DB 01H __5AB313A4_winerror@h DB 01H __B7E7187B_timezoneapi@h DB 01H __6DE9EB6F_winbase@h DB 01H __56B2AFF2_wingdi@h DB 01H __BA1161A9_tvout@h DB 01H __0501A018_winuser@h DB 01H __EF12FA99_datetimeapi@h DB 01H __8FA7C3CA_winnls@h DB 01H __390F0C47_stringapiset@h DB 01H __28605B0A_wincontypes@h DB 01H __BFBDE86D_consoleapi@h DB 01H __C3CAFBF0_consoleapi2@h DB 01H __C20891C7_consoleapi3@h DB 01H __717C98B6_wincon@h DB 01H __2884C177_verrsrc@h DB 01H __A3FD3A34_winver@h DB 01H __6F8AD9F1_reason@h DB 01H __4C90FD6F_winreg@h DB 01H __68AFEBAD_wnnc@h DB 01H __5A7AB086_winnetwk@h DB 01H __2FE8A10C_stralign@h DB 01H __34558472_winsvc@h DB 01H __058845F1_mcx@h DB 01H __7F16006B_ime_cmodes@h DB 01H __0A3AF599_imm@h DB 01H __9349FE86_windows@h DB 01H __639A050C_sn_internal@h DB 01H __836A8CFC_stdint@h DB 01H __714FE6D7_sn_target@h DB 01H __60B45B40_corecrt_stdio_config@h DB 01H __CFA3741E_corecrt_wstdio@h DB 01H __B3FE3303_stdio@h DB 01H __955456CD_stddef@h DB 01H __99AED4FB_corecrt_search@h DB 01H __8B813BF6_corecrt_wstdlib@h DB 01H __3D1CA2C3_limits@h DB 01H __E8FB0A68_stdlib@h DB 01H __F562FA57_stb_image@h DB 01H __C95DC661_khrplatform@h DB 01H __6C577136_gl@h DB 01H __EE638A2C_wgl@h DB 01H __8EF9E35C_glfw3@h DB 01H __F8AC8404_emmintrin@h DB 01H __270DEC8D_pmmintrin@h DB 01H __97D49F0F_tmmintrin@h DB 01H __BEEF8A8C_smmintrin@h DB 01H __DB8D0340_nmmintrin@h DB 01H __0E36F90E_wmmintrin@h DB 01H __C5A2B409_zmmintrin@h DB 01H __F2B616C3_immintrin@h DB 01H __9FB25DBE_assert@h DB 01H __4E664295_glfw_function@h DB 01H __64C0EF11_StgSharpNative@h DB 01H __E2EC0CAF_sn_matkernel@h DB 01H __47E843D2_intrin0@inl@h DB 01H __130964FF_setjmp@h DB 01H __4875F786_ammintrin@h DB 01H __353FD888_intrin@h DB 01H __5FE1E9E3_isa_availability@h DB 01H __AA840D82_sn_intrinsic@h DB 01H __CE29950A_sn_intrincontext@x86@h DB 01H __3EBA305F_simdid@x86@c DB 01H msvcjmc ENDS PUBLIC sn_get_simd_level_global PUBLIC sn_get_simd_level_local PUBLIC __JustMyCode_Default PUBLIC ??_C@_0N@IGLDKOMM@HygonGenuine@ ; `string' PUBLIC ??_C@_0N@FFJGBINN@AuthenticAMD@ ; `string' PUBLIC ??_C@_0N@BDDFKIGD@GenuineIntel@ ; `string' PUBLIC ??_C@_0N@DHAFJCOO@CentaurHauls@ ; `string' PUBLIC ??_C@_0N@BDNCIKNF@?5?5Shanghai?5?5@ ; `string' EXTRN __report_rangecheckfailure:PROC EXTRN memcmp:PROC EXTRN strcmp:PROC EXTRN _RTC_CheckStackVars:PROC EXTRN _RTC_InitBase:PROC EXTRN _RTC_Shutdown:PROC EXTRN __CheckForDebuggerJustMyCode:PROC EXTRN __GSHandlerCheck:PROC EXTRN __security_check_cookie:PROC EXTRN __security_cookie:QWORD _BSS SEGMENT global_simdid DQ 01H DUP (?) _BSS ENDS ; COMDAT pdata pdata SEGMENT $pdata$sn_get_simd_level_global DD imagerel $LN4 DD imagerel $LN4+76 DD imagerel $unwind$sn_get_simd_level_global pdata ENDS ; COMDAT pdata pdata SEGMENT $pdata$sn_get_simd_level_local DD imagerel $LN98 DD imagerel $LN98+3276 DD imagerel $unwind$sn_get_simd_level_local pdata ENDS ; COMDAT pdata pdata SEGMENT $pdata$get_cpuid DD imagerel get_cpuid DD imagerel get_cpuid+250 DD imagerel $unwind$get_cpuid pdata ENDS ; COMDAT pdata pdata SEGMENT $pdata$xgetbv_has_xmm_ymm DD imagerel xgetbv_has_xmm_ymm DD imagerel xgetbv_has_xmm_ymm+99 DD imagerel $unwind$xgetbv_has_xmm_ymm pdata ENDS ; COMDAT pdata pdata SEGMENT $pdata$xgetbv_has_avx512_state DD imagerel xgetbv_has_avx512_state DD imagerel xgetbv_has_avx512_state+113 DD imagerel $unwind$xgetbv_has_avx512_state pdata ENDS ; COMDAT pdata pdata SEGMENT $pdata$amd_avx512_impl DD imagerel amd_avx512_impl DD imagerel amd_avx512_impl+75 DD imagerel $unwind$amd_avx512_impl pdata ENDS ; COMDAT pdata pdata SEGMENT $pdata$is_amd_glue_ymm DD imagerel is_amd_glue_ymm DD imagerel is_amd_glue_ymm+277 DD imagerel $unwind$is_amd_glue_ymm pdata ENDS ; COMDAT rtc$TMZ rtc$TMZ SEGMENT _RTC_Shutdown.rtc$TMZ DQ FLAT:_RTC_Shutdown rtc$TMZ ENDS ; COMDAT rtc$IMZ rtc$IMZ SEGMENT _RTC_InitBase.rtc$IMZ DQ FLAT:_RTC_InitBase rtc$IMZ ENDS ; COMDAT ??_C@_0N@BDNCIKNF@?5?5Shanghai?5?5@ CONST SEGMENT ??_C@_0N@BDNCIKNF@?5?5Shanghai?5?5@ DB ' Shanghai ', 00H ; `string' CONST ENDS ; COMDAT ??_C@_0N@DHAFJCOO@CentaurHauls@ CONST SEGMENT ??_C@_0N@DHAFJCOO@CentaurHauls@ DB 'CentaurHauls', 00H ; `string' CONST ENDS ; COMDAT ??_C@_0N@BDDFKIGD@GenuineIntel@ CONST SEGMENT ??_C@_0N@BDDFKIGD@GenuineIntel@ DB 'GenuineIntel', 00H ; `string' CONST ENDS ; COMDAT ??_C@_0N@FFJGBINN@AuthenticAMD@ CONST SEGMENT ??_C@_0N@FFJGBINN@AuthenticAMD@ DB 'AuthenticAMD', 00H ; `string' CONST ENDS ; COMDAT ??_C@_0N@IGLDKOMM@HygonGenuine@ CONST SEGMENT ??_C@_0N@IGLDKOMM@HygonGenuine@ DB 'HygonGenuine', 00H ; `string' CONST ENDS ; COMDAT xdata xdata SEGMENT $unwind$is_amd_glue_ymm DD 025051701H DD 01122317H DD 0700b0035H DD 0500aH xdata ENDS ; COMDAT xdata xdata SEGMENT $unwind$amd_avx512_impl DD 025051201H DD 010d2312H DD 07006001dH DD 05005H xdata ENDS ; COMDAT xdata xdata SEGMENT $unwind$xgetbv_has_avx512_state DD 025050f01H DD 010a230fH DD 070030025H DD 05002H xdata ENDS ; COMDAT xdata xdata SEGMENT $unwind$xgetbv_has_xmm_ymm DD 025050f01H DD 010a230fH DD 070030021H DD 05002H xdata ENDS ; COMDAT voltbl voltbl SEGMENT _volmd DB 043H DB 0e0H voltbl ENDS ; COMDAT xdata xdata SEGMENT $unwind$get_cpuid DD 025064a19H DD 011c2321H DD 070150022H DD 050133014H DD imagerel __GSHandlerCheck DD 0108H xdata ENDS ; COMDAT CONST CONST SEGMENT get_cpuid$rtcName$0 DB 072H DB 065H DB 067H DB 073H DB 00H ORG $+11 get_cpuid$rtcVarDesc DD 028H DD 010H DQ FLAT:get_cpuid$rtcName$0 ORG $+48 get_cpuid$rtcFrameData DD 01H DD 00H DQ FLAT:get_cpuid$rtcVarDesc CONST ENDS ; COMDAT voltbl voltbl SEGMENT _volmd DW 02aH DW 0cb3H voltbl ENDS ; COMDAT xdata xdata SEGMENT $unwind$sn_get_simd_level_local DD 035053119H DD 010a330fH DD 070030143H DD 05002H DD imagerel __GSHandlerCheck DD 0a08H xdata ENDS ; COMDAT CONST CONST SEGMENT sn_get_simd_level_local$rtcName$0 DB 05fH DB 073H DB 069H DB 06dH DB 064H DB 069H DB 064H DB 00H sn_get_simd_level_local$rtcName$1 DB 065H DB 061H DB 078H DB 00H sn_get_simd_level_local$rtcName$2 DB 065H DB 062H DB 078H DB 00H sn_get_simd_level_local$rtcName$3 DB 065H DB 063H DB 078H DB 00H sn_get_simd_level_local$rtcName$4 DB 065H DB 064H DB 078H DB 00H sn_get_simd_level_local$rtcName$5 DB 076H DB 065H DB 06eH DB 064H DB 06fH DB 072H DB 00H ORG $+1 sn_get_simd_level_local$rtcName$6 DB 061H DB 031H DB 030H DB 05fH DB 065H DB 061H DB 078H DB 00H sn_get_simd_level_local$rtcName$7 DB 061H DB 031H DB 030H DB 05fH DB 065H DB 062H DB 078H DB 00H sn_get_simd_level_local$rtcName$8 DB 061H DB 031H DB 030H DB 05fH DB 065H DB 063H DB 078H DB 00H sn_get_simd_level_local$rtcName$9 DB 061H DB 031H DB 030H DB 05fH DB 065H DB 064H DB 078H DB 00H sn_get_simd_level_local$rtcName$10 DB 068H DB 05fH DB 065H DB 061H DB 078H DB 00H ORG $+2 sn_get_simd_level_local$rtcName$11 DB 068H DB 05fH DB 065H DB 062H DB 078H DB 00H ORG $+2 sn_get_simd_level_local$rtcName$12 DB 068H DB 05fH DB 065H DB 063H DB 078H DB 00H ORG $+2 sn_get_simd_level_local$rtcName$13 DB 068H DB 05fH DB 065H DB 064H DB 078H DB 00H ORG $+2 sn_get_simd_level_local$rtcVarDesc DD 06a4H DD 04H DQ FLAT:sn_get_simd_level_local$rtcName$13 DD 0684H DD 04H DQ FLAT:sn_get_simd_level_local$rtcName$12 DD 0664H DD 04H DQ FLAT:sn_get_simd_level_local$rtcName$11 DD 0644H DD 04H DQ FLAT:sn_get_simd_level_local$rtcName$10 DD 05e4H DD 04H DQ FLAT:sn_get_simd_level_local$rtcName$9 DD 05c4H DD 04H DQ FLAT:sn_get_simd_level_local$rtcName$8 DD 05a4H DD 04H DQ FLAT:sn_get_simd_level_local$rtcName$7 DD 0584H DD 04H DQ FLAT:sn_get_simd_level_local$rtcName$6 DD 0d8H DD 0dH DQ FLAT:sn_get_simd_level_local$rtcName$5 DD 0b4H DD 04H DQ FLAT:sn_get_simd_level_local$rtcName$4 DD 094H DD 04H DQ FLAT:sn_get_simd_level_local$rtcName$3 DD 074H DD 04H DQ FLAT:sn_get_simd_level_local$rtcName$2 DD 054H DD 04H DQ FLAT:sn_get_simd_level_local$rtcName$1 DD 038H DD 08H DQ FLAT:sn_get_simd_level_local$rtcName$0 ORG $+672 sn_get_simd_level_local$rtcFrameData DD 0eH DD 00H DQ FLAT:sn_get_simd_level_local$rtcVarDesc CONST ENDS ; COMDAT xdata xdata SEGMENT $unwind$sn_get_simd_level_global DD 025050f01H DD 010a230fH DD 07003001dH DD 05002H xdata ENDS ; Function compile flags: /Odt ; COMDAT __JustMyCode_Default _TEXT SEGMENT __JustMyCode_Default PROC ; COMDAT 00000 c2 00 00 ret 0 __JustMyCode_Default ENDP _TEXT ENDS ; Function compile flags: /Odtp /RTCsu /ZI ; File D:\platform-dev\StgSharp.Native\sn-src\simdid.x86.c ; COMDAT is_amd_glue_ymm _TEXT SEGMENT base_fam$ = 4 ext_fam$ = 36 disp_fam$ = 68 base_mdl$ = 100 ext_mdl$ = 132 disp_mdl$ = 164 tv78 = 372 tv87 = 372 vendor$ = 416 cpuid1_eax$ = 424 is_amd_glue_ymm PROC ; COMDAT ; 76 : { 00000 89 54 24 10 mov DWORD PTR [rsp+16], edx 00004 48 89 4c 24 08 mov QWORD PTR [rsp+8], rcx 00009 55 push rbp 0000a 57 push rdi 0000b 48 81 ec a8 01 00 00 sub rsp, 424 ; 000001a8H 00012 48 8d 6c 24 20 lea rbp, QWORD PTR [rsp+32] 00017 48 8d 0d 00 00 00 00 lea rcx, OFFSET FLAT:__3EBA305F_simdid@x86@c 0001e e8 00 00 00 00 call __CheckForDebuggerJustMyCode 00023 90 npad 1 ; 77 : if (strcmp(vendor, "HygonGenuine") == 0) 00024 48 8d 15 00 00 00 00 lea rdx, OFFSET FLAT:??_C@_0N@IGLDKOMM@HygonGenuine@ 0002b 48 8b 8d a0 01 00 00 mov rcx, QWORD PTR vendor$[rbp] 00032 e8 00 00 00 00 call strcmp 00037 85 c0 test eax, eax 00039 75 0a jne SHORT $LN2@is_amd_glu ; 78 : return 1; /* Hygon is Zen1-based; always split YMM */ 0003b b8 01 00 00 00 mov eax, 1 00040 e9 c6 00 00 00 jmp $LN1@is_amd_glu $LN2@is_amd_glu: ; 79 : if (strcmp(vendor, "AuthenticAMD") != 0) 00045 48 8d 15 00 00 00 00 lea rdx, OFFSET FLAT:??_C@_0N@FFJGBINN@AuthenticAMD@ 0004c 48 8b 8d a0 01 00 00 mov rcx, QWORD PTR vendor$[rbp] 00053 e8 00 00 00 00 call strcmp 00058 85 c0 test eax, eax 0005a 74 07 je SHORT $LN3@is_amd_glu ; 80 : return 0; 0005c 33 c0 xor eax, eax 0005e e9 a8 00 00 00 jmp $LN1@is_amd_glu $LN3@is_amd_glu: ; 81 : int base_fam = (cpuid1_eax >> 8) & 0xF; 00063 8b 85 a8 01 00 00 mov eax, DWORD PTR cpuid1_eax$[rbp] 00069 c1 f8 08 sar eax, 8 0006c 83 e0 0f and eax, 15 0006f 89 45 04 mov DWORD PTR base_fam$[rbp], eax ; 82 : int ext_fam = (cpuid1_eax >> 20) & 0xFF; 00072 8b 85 a8 01 00 00 mov eax, DWORD PTR cpuid1_eax$[rbp] 00078 c1 f8 14 sar eax, 20 0007b 25 ff 00 00 00 and eax, 255 ; 000000ffH 00080 89 45 24 mov DWORD PTR ext_fam$[rbp], eax ; 83 : int disp_fam = (base_fam < 0xF) ? base_fam : (base_fam + ext_fam); 00083 83 7d 04 0f cmp DWORD PTR base_fam$[rbp], 15 00087 7d 0b jge SHORT $LN5@is_amd_glu 00089 8b 45 04 mov eax, DWORD PTR base_fam$[rbp] 0008c 89 85 74 01 00 00 mov DWORD PTR tv78[rbp], eax 00092 eb 10 jmp SHORT $LN6@is_amd_glu $LN5@is_amd_glu: 00094 8b 45 24 mov eax, DWORD PTR ext_fam$[rbp] 00097 8b 4d 04 mov ecx, DWORD PTR base_fam$[rbp] 0009a 03 c8 add ecx, eax 0009c 8b c1 mov eax, ecx 0009e 89 85 74 01 00 00 mov DWORD PTR tv78[rbp], eax $LN6@is_amd_glu: 000a4 8b 85 74 01 00 00 mov eax, DWORD PTR tv78[rbp] 000aa 89 45 44 mov DWORD PTR disp_fam$[rbp], eax ; 84 : int base_mdl = (cpuid1_eax >> 4) & 0xF; 000ad 8b 85 a8 01 00 00 mov eax, DWORD PTR cpuid1_eax$[rbp] 000b3 c1 f8 04 sar eax, 4 000b6 83 e0 0f and eax, 15 000b9 89 45 64 mov DWORD PTR base_mdl$[rbp], eax ; 85 : int ext_mdl = (cpuid1_eax >> 16) & 0xF; 000bc 8b 85 a8 01 00 00 mov eax, DWORD PTR cpuid1_eax$[rbp] 000c2 c1 f8 10 sar eax, 16 000c5 83 e0 0f and eax, 15 000c8 89 85 84 00 00 00 mov DWORD PTR ext_mdl$[rbp], eax ; 86 : int disp_mdl = (ext_mdl << 4) | base_mdl; 000ce 8b 85 84 00 00 00 mov eax, DWORD PTR ext_mdl$[rbp] 000d4 c1 e0 04 shl eax, 4 000d7 0b 45 64 or eax, DWORD PTR base_mdl$[rbp] 000da 89 85 a4 00 00 00 mov DWORD PTR disp_mdl$[rbp], eax ; 87 : return (disp_fam == 0x17) && (disp_mdl < 0x30); /* Zen1/Zen+ */ 000e0 83 7d 44 17 cmp DWORD PTR disp_fam$[rbp], 23 000e4 75 15 jne SHORT $LN7@is_amd_glu 000e6 83 bd a4 00 00 00 30 cmp DWORD PTR disp_mdl$[rbp], 48 ; 00000030H 000ed 7d 0c jge SHORT $LN7@is_amd_glu 000ef c7 85 74 01 00 00 01 00 00 00 mov DWORD PTR tv87[rbp], 1 000f9 eb 0a jmp SHORT $LN8@is_amd_glu $LN7@is_amd_glu: 000fb c7 85 74 01 00 00 00 00 00 00 mov DWORD PTR tv87[rbp], 0 $LN8@is_amd_glu: 00105 8b 85 74 01 00 00 mov eax, DWORD PTR tv87[rbp] $LN1@is_amd_glu: ; 88 : } 0010b 48 8d a5 88 01 00 00 lea rsp, QWORD PTR [rbp+392] 00112 5f pop rdi 00113 5d pop rbp 00114 c3 ret 0 is_amd_glue_ymm ENDP _TEXT ENDS ; Function compile flags: /Odtp /RTCsu /ZI ; File D:\platform-dev\StgSharp.Native\sn-src\simdid.x86.c ; COMDAT amd_avx512_impl _TEXT SEGMENT family$ = 224 amd_avx512_impl PROC ; COMDAT ; 65 : { 00000 89 4c 24 08 mov DWORD PTR [rsp+8], ecx 00004 55 push rbp 00005 57 push rdi 00006 48 81 ec e8 00 00 00 sub rsp, 232 ; 000000e8H 0000d 48 8d 6c 24 20 lea rbp, QWORD PTR [rsp+32] 00012 48 8d 0d 00 00 00 00 lea rcx, OFFSET FLAT:__3EBA305F_simdid@x86@c 00019 e8 00 00 00 00 call __CheckForDebuggerJustMyCode 0001e 90 npad 1 ; 66 : if (family == 0x19) return SIMDID_AVX512_IMPL_DUAL; 0001f 83 bd e0 00 00 00 19 cmp DWORD PTR family$[rbp], 25 00026 75 07 jne SHORT $LN2@amd_avx512 00028 b8 40 00 00 00 mov eax, 64 ; 00000040H 0002d eb 12 jmp SHORT $LN1@amd_avx512 $LN2@amd_avx512: ; 67 : if (family >= 0x1A) return SIMDID_AVX512_IMPL_NATIVE; 0002f 83 bd e0 00 00 00 1a cmp DWORD PTR family$[rbp], 26 00036 7c 07 jl SHORT $LN3@amd_avx512 00038 b8 80 00 00 00 mov eax, 128 ; 00000080H 0003d eb 02 jmp SHORT $LN1@amd_avx512 $LN3@amd_avx512: ; 68 : return SIMDID_AVX512_IMPL_UNKNOWN; 0003f 33 c0 xor eax, eax $LN1@amd_avx512: ; 69 : } 00041 48 8d a5 c8 00 00 00 lea rsp, QWORD PTR [rbp+200] 00048 5f pop rdi 00049 5d pop rbp 0004a c3 ret 0 amd_avx512_impl ENDP _TEXT ENDS ; Function compile flags: /Odtp /RTCsu /ZI ; File D:\platform-dev\StgSharp.Native\sn-src\simdid.x86.c ; COMDAT xgetbv_has_avx512_state _TEXT SEGMENT mask$ = 8 xcr0$ = 40 tv68 = 244 xgetbv_has_avx512_state PROC ; COMDAT ; 49 : { 00000 40 55 push rbp 00002 57 push rdi 00003 48 81 ec 28 01 00 00 sub rsp, 296 ; 00000128H 0000a 48 8d 6c 24 20 lea rbp, QWORD PTR [rsp+32] 0000f 48 8d 0d 00 00 00 00 lea rcx, OFFSET FLAT:__3EBA305F_simdid@x86@c 00016 e8 00 00 00 00 call __CheckForDebuggerJustMyCode 0001b 90 npad 1 ; 50 : const unsigned long long mask = (1ull << 0) | (1ull << 1) | (1ull << 2) | (1ull << 5) | 0001c 48 c7 45 08 67 00 00 00 mov QWORD PTR mask$[rbp], 103 ; 00000067H ; 51 : (1ull << 6); ; 52 : #if defined(_MSC_VER) ; 53 : unsigned __int64 xcr0 = _xgetbv(0); 00024 33 c9 xor ecx, ecx 00026 0f 01 d0 xgetbv 00029 48 c1 e2 20 shl rdx, 32 ; 00000020H 0002d 48 0b d0 or rdx, rax 00030 48 8b c2 mov rax, rdx 00033 48 89 45 28 mov QWORD PTR xcr0$[rbp], rax ; 54 : #else ; 55 : unsigned long long xcr0 = __builtin_ia32_xgetbv(0); ; 56 : #endif ; 57 : return ((xcr0 & mask) == mask); 00037 48 8b 45 08 mov rax, QWORD PTR mask$[rbp] 0003b 48 8b 4d 28 mov rcx, QWORD PTR xcr0$[rbp] 0003f 48 23 c8 and rcx, rax 00042 48 8b c1 mov rax, rcx 00045 48 3b 45 08 cmp rax, QWORD PTR mask$[rbp] 00049 75 0c jne SHORT $LN3@xgetbv_has 0004b c7 85 f4 00 00 00 01 00 00 00 mov DWORD PTR tv68[rbp], 1 00055 eb 0a jmp SHORT $LN4@xgetbv_has $LN3@xgetbv_has: 00057 c7 85 f4 00 00 00 00 00 00 00 mov DWORD PTR tv68[rbp], 0 $LN4@xgetbv_has: 00061 8b 85 f4 00 00 00 mov eax, DWORD PTR tv68[rbp] ; 58 : } 00067 48 8d a5 08 01 00 00 lea rsp, QWORD PTR [rbp+264] 0006e 5f pop rdi 0006f 5d pop rbp 00070 c3 ret 0 xgetbv_has_avx512_state ENDP _TEXT ENDS ; Function compile flags: /Odtp /RTCsu /ZI ; File D:\platform-dev\StgSharp.Native\sn-src\simdid.x86.c ; COMDAT xgetbv_has_xmm_ymm _TEXT SEGMENT xcr0$ = 8 tv68 = 212 xgetbv_has_xmm_ymm PROC ; COMDAT ; 39 : { 00000 40 55 push rbp 00002 57 push rdi 00003 48 81 ec 08 01 00 00 sub rsp, 264 ; 00000108H 0000a 48 8d 6c 24 20 lea rbp, QWORD PTR [rsp+32] 0000f 48 8d 0d 00 00 00 00 lea rcx, OFFSET FLAT:__3EBA305F_simdid@x86@c 00016 e8 00 00 00 00 call __CheckForDebuggerJustMyCode 0001b 90 npad 1 ; 40 : #if defined(_MSC_VER) ; 41 : unsigned __int64 xcr0 = _xgetbv(0); 0001c 33 c9 xor ecx, ecx 0001e 0f 01 d0 xgetbv 00021 48 c1 e2 20 shl rdx, 32 ; 00000020H 00025 48 0b d0 or rdx, rax 00028 48 8b c2 mov rax, rdx 0002b 48 89 45 08 mov QWORD PTR xcr0$[rbp], rax ; 42 : #else ; 43 : unsigned long long xcr0 = __builtin_ia32_xgetbv(0); ; 44 : #endif ; 45 : return ((xcr0 & 0x6) == 0x6); 0002f 48 8b 45 08 mov rax, QWORD PTR xcr0$[rbp] 00033 48 83 e0 06 and rax, 6 00037 48 83 f8 06 cmp rax, 6 0003b 75 0c jne SHORT $LN3@xgetbv_has 0003d c7 85 d4 00 00 00 01 00 00 00 mov DWORD PTR tv68[rbp], 1 00047 eb 0a jmp SHORT $LN4@xgetbv_has $LN3@xgetbv_has: 00049 c7 85 d4 00 00 00 00 00 00 00 mov DWORD PTR tv68[rbp], 0 $LN4@xgetbv_has: 00053 8b 85 d4 00 00 00 mov eax, DWORD PTR tv68[rbp] ; 46 : } 00059 48 8d a5 e8 00 00 00 lea rsp, QWORD PTR [rbp+232] 00060 5f pop rdi 00061 5d pop rbp 00062 c3 ret 0 xgetbv_has_xmm_ymm ENDP _TEXT ENDS ; Function compile flags: /Odtp /RTCsu /ZI ; File D:\platform-dev\StgSharp.Native\sn-src\simdid.x86.c ; COMDAT get_cpuid _TEXT SEGMENT regs$ = 8 __$ArrayPad$ = 232 leaf$ = 272 subleaf$ = 280 eax$ = 288 ebx$ = 296 ecx$ = 304 edx$ = 312 get_cpuid PROC ; COMDAT ; 20 : { 00000 4c 89 4c 24 20 mov QWORD PTR [rsp+32], r9 00005 4c 89 44 24 18 mov QWORD PTR [rsp+24], r8 0000a 89 54 24 10 mov DWORD PTR [rsp+16], edx 0000e 89 4c 24 08 mov DWORD PTR [rsp+8], ecx 00012 55 push rbp 00013 53 push rbx 00014 57 push rdi 00015 48 81 ec 10 01 00 00 sub rsp, 272 ; 00000110H 0001c 48 8d 6c 24 20 lea rbp, QWORD PTR [rsp+32] 00021 48 8d 7c 24 20 lea rdi, QWORD PTR [rsp+32] 00026 b9 0c 00 00 00 mov ecx, 12 0002b b8 cc cc cc cc mov eax, -858993460 ; ccccccccH 00030 f3 ab rep stosd 00032 8b 8c 24 38 01 00 00 mov ecx, DWORD PTR [rsp+312] 00039 48 8b 05 00 00 00 00 mov rax, QWORD PTR __security_cookie 00040 48 33 c5 xor rax, rbp 00043 48 89 85 e8 00 00 00 mov QWORD PTR __$ArrayPad$[rbp], rax 0004a 48 8d 0d 00 00 00 00 lea rcx, OFFSET FLAT:__3EBA305F_simdid@x86@c 00051 e8 00 00 00 00 call __CheckForDebuggerJustMyCode 00056 90 npad 1 ; 21 : #if defined(_MSC_VER) ; 22 : int regs[4]; ; 23 : __cpuidex(regs, leaf, subleaf); 00057 8b 85 10 01 00 00 mov eax, DWORD PTR leaf$[rbp] 0005d 8b 8d 18 01 00 00 mov ecx, DWORD PTR subleaf$[rbp] 00063 0f a2 cpuid 00065 4c 8d 45 08 lea r8, QWORD PTR regs$[rbp] 00069 41 89 00 mov DWORD PTR [r8], eax 0006c 41 89 58 04 mov DWORD PTR [r8+4], ebx 00070 41 89 48 08 mov DWORD PTR [r8+8], ecx 00074 41 89 50 0c mov DWORD PTR [r8+12], edx ; 24 : *eax = regs[0]; 00078 b8 04 00 00 00 mov eax, 4 0007d 48 6b c0 00 imul rax, rax, 0 00081 48 8b 8d 20 01 00 00 mov rcx, QWORD PTR eax$[rbp] 00088 8b 44 05 08 mov eax, DWORD PTR regs$[rbp+rax] 0008c 89 01 mov DWORD PTR [rcx], eax ; 25 : *ebx = regs[1]; 0008e b8 04 00 00 00 mov eax, 4 00093 48 6b c0 01 imul rax, rax, 1 00097 48 8b 8d 28 01 00 00 mov rcx, QWORD PTR ebx$[rbp] 0009e 8b 44 05 08 mov eax, DWORD PTR regs$[rbp+rax] 000a2 89 01 mov DWORD PTR [rcx], eax ; 26 : *ecx = regs[2]; 000a4 b8 04 00 00 00 mov eax, 4 000a9 48 6b c0 02 imul rax, rax, 2 000ad 48 8b 8d 30 01 00 00 mov rcx, QWORD PTR ecx$[rbp] 000b4 8b 44 05 08 mov eax, DWORD PTR regs$[rbp+rax] 000b8 89 01 mov DWORD PTR [rcx], eax ; 27 : *edx = regs[3]; 000ba b8 04 00 00 00 mov eax, 4 000bf 48 6b c0 03 imul rax, rax, 3 000c3 48 8b 8d 38 01 00 00 mov rcx, QWORD PTR edx$[rbp] 000ca 8b 44 05 08 mov eax, DWORD PTR regs$[rbp+rax] 000ce 89 01 mov DWORD PTR [rcx], eax ; 28 : #else ; 29 : unsigned int a, b, c, d; ; 30 : __cpuid_count((unsigned int)leaf, (unsigned int)subleaf, a, b, c, d); ; 31 : *eax = (int)a; ; 32 : *ebx = (int)b; ; 33 : *ecx = (int)c; ; 34 : *edx = (int)d; ; 35 : #endif ; 36 : } 000d0 48 8d 4d e0 lea rcx, QWORD PTR [rbp-32] 000d4 48 8d 15 00 00 00 00 lea rdx, OFFSET FLAT:get_cpuid$rtcFrameData 000db e8 00 00 00 00 call _RTC_CheckStackVars 000e0 48 8b 8d e8 00 00 00 mov rcx, QWORD PTR __$ArrayPad$[rbp] 000e7 48 33 cd xor rcx, rbp 000ea e8 00 00 00 00 call __security_check_cookie 000ef 48 8d a5 f0 00 00 00 lea rsp, QWORD PTR [rbp+240] 000f6 5f pop rdi 000f7 5b pop rbx 000f8 5d pop rbp 000f9 c3 ret 0 get_cpuid ENDP _TEXT ENDS ; Function compile flags: /Odtp /RTCsu /ZI ; File D:\platform-dev\StgSharp.Native\sn-src\simdid.x86.c ; COMDAT sn_get_simd_level_local _TEXT SEGMENT _simdid$ = 8 eax$ = 36 ebx$ = 68 ecx$ = 100 edx$ = 132 vendor$ = 168 is_intel$ = 212 is_amd$ = 244 is_hygon$ = 276 is_via$ = 308 cpuid1_eax$ = 340 family$ = 372 model$ = 404 has_sse42$ = 436 has_avx$ = 468 has_osxsave$ = 500 has_fma$ = 532 has_f16c$ = 564 root$ = 600 manu$ = 632 main_lvl$ = 664 avx512_bits$ = 696 amx_bits$ = 728 avx_bits$ = 760 avx10_bits$ = 792 has_hybrid$ = 820 has_bmi1$17 = 852 has_bmi2$18 = 884 has_avx2$19 = 916 has_avx512f$20 = 948 has_avx512dq$21 = 980 has_avx512bw$22 = 1012 has_avx512vl$23 = 1044 has_avx512_vnni$24 = 1076 has_vbmi$25 = 1108 has_vbmi2$26 = 1140 has_amx_tile$27 = 1172 has_amx_int8$28 = 1204 has_amx_bf16$29 = 1236 has_bf16$30 = 1268 has_fp16$31 = 1300 has_avx10$32 = 1332 a10_eax$33 = 1364 a10_ebx$34 = 1396 a10_ecx$35 = 1428 a10_edx$36 = 1460 avx10_ver$37 = 1492 uarch_bits$ = 1528 h_eax$38 = 1556 h_ebx$39 = 1588 h_ecx$40 = 1620 h_edx$41 = 1652 core_type$42 = 1684 $T43 = 2488 tv208 = 2500 tv282 = 2500 tv285 = 2500 tv170 = 2500 tv167 = 2500 tv164 = 2500 tv161 = 2500 tv158 = 2500 tv139 = 2500 tv129 = 2500 tv87 = 2500 tv178 = 2500 tv202 = 2500 tv205 = 2500 tv288 = 2500 tv211 = 2500 tv214 = 2500 tv217 = 2500 tv220 = 2500 tv223 = 2500 tv92 = 2500 tv258 = 2500 tv261 = 2500 tv264 = 2500 tv267 = 2500 tv270 = 2500 tv273 = 2500 tv176 = 2504 tv174 = 2508 tv172 = 2512 __$ArrayPad$ = 2520 sn_get_simd_level_local PROC ; COMDAT ; 91 : { $LN98: 00000 40 55 push rbp 00002 57 push rdi 00003 48 81 ec 18 0a 00 00 sub rsp, 2584 ; 00000a18H 0000a 48 8d 6c 24 30 lea rbp, QWORD PTR [rsp+48] 0000f 48 8d 7c 24 30 lea rdi, QWORD PTR [rsp+48] 00014 b9 ba 01 00 00 mov ecx, 442 ; 000001baH 00019 b8 cc cc cc cc mov eax, -858993460 ; ccccccccH 0001e f3 ab rep stosd 00020 48 8b 05 00 00 00 00 mov rax, QWORD PTR __security_cookie 00027 48 33 c5 xor rax, rbp 0002a 48 89 85 d8 09 00 00 mov QWORD PTR __$ArrayPad$[rbp], rax 00031 48 8d 0d 00 00 00 00 lea rcx, OFFSET FLAT:__3EBA305F_simdid@x86@c 00038 e8 00 00 00 00 call __CheckForDebuggerJustMyCode 0003d 90 npad 1 ; 92 : SIMDID _simdid = { 0 }; 0003e 48 8d 45 08 lea rax, QWORD PTR _simdid$[rbp] 00042 48 8b f8 mov rdi, rax 00045 33 c0 xor eax, eax 00047 b9 08 00 00 00 mov ecx, 8 0004c f3 aa rep stosb ; 93 : ; 94 : int eax = 0, ebx = 0, ecx = 0, edx = 0; 0004e c7 45 24 00 00 00 00 mov DWORD PTR eax$[rbp], 0 00055 c7 45 44 00 00 00 00 mov DWORD PTR ebx$[rbp], 0 0005c c7 45 64 00 00 00 00 mov DWORD PTR ecx$[rbp], 0 00063 c7 85 84 00 00 00 00 00 00 00 mov DWORD PTR edx$[rbp], 0 ; 95 : ; 96 : /* Vendor */ ; 97 : get_cpuid(0, 0, &eax, &ebx, &ecx, &edx); 0006d 48 8d 85 84 00 00 00 lea rax, QWORD PTR edx$[rbp] 00074 48 89 44 24 28 mov QWORD PTR [rsp+40], rax 00079 48 8d 45 64 lea rax, QWORD PTR ecx$[rbp] 0007d 48 89 44 24 20 mov QWORD PTR [rsp+32], rax 00082 4c 8d 4d 44 lea r9, QWORD PTR ebx$[rbp] 00086 4c 8d 45 24 lea r8, QWORD PTR eax$[rbp] 0008a 33 d2 xor edx, edx 0008c 33 c9 xor ecx, ecx 0008e e8 00 00 00 00 call get_cpuid 00093 90 npad 1 ; 98 : char vendor[13]; ; 99 : ((int *)vendor)[0] = ebx; 00094 b8 04 00 00 00 mov eax, 4 00099 48 6b c0 00 imul rax, rax, 0 0009d 8b 4d 44 mov ecx, DWORD PTR ebx$[rbp] 000a0 89 8c 05 a8 00 00 00 mov DWORD PTR vendor$[rbp+rax], ecx ; 100 : ((int *)vendor)[1] = edx; 000a7 b8 04 00 00 00 mov eax, 4 000ac 48 6b c0 01 imul rax, rax, 1 000b0 8b 8d 84 00 00 00 mov ecx, DWORD PTR edx$[rbp] 000b6 89 8c 05 a8 00 00 00 mov DWORD PTR vendor$[rbp+rax], ecx ; 101 : ((int *)vendor)[2] = ecx; 000bd b8 04 00 00 00 mov eax, 4 000c2 48 6b c0 02 imul rax, rax, 2 000c6 8b 4d 64 mov ecx, DWORD PTR ecx$[rbp] 000c9 89 8c 05 a8 00 00 00 mov DWORD PTR vendor$[rbp+rax], ecx ; 102 : vendor[12] = '\0'; 000d0 b8 01 00 00 00 mov eax, 1 000d5 48 6b c0 0c imul rax, rax, 12 000d9 48 89 85 b8 09 00 00 mov QWORD PTR $T43[rbp], rax 000e0 48 83 bd b8 09 00 00 0d cmp QWORD PTR $T43[rbp], 13 000e8 73 02 jae SHORT $LN36@sn_get_sim 000ea eb 06 jmp SHORT $LN37@sn_get_sim $LN36@sn_get_sim: 000ec e8 00 00 00 00 call __report_rangecheckfailure 000f1 90 npad 1 $LN37@sn_get_sim: 000f2 48 8b 85 b8 09 00 00 mov rax, QWORD PTR $T43[rbp] 000f9 c6 84 05 a8 00 00 00 00 mov BYTE PTR vendor$[rbp+rax], 0 ; 103 : const int is_intel = (strcmp(vendor, "GenuineIntel") == 0); 00101 48 8d 15 00 00 00 00 lea rdx, OFFSET FLAT:??_C@_0N@BDDFKIGD@GenuineIntel@ 00108 48 8d 8d a8 00 00 00 lea rcx, QWORD PTR vendor$[rbp] 0010f e8 00 00 00 00 call strcmp 00114 85 c0 test eax, eax 00116 75 0c jne SHORT $LN38@sn_get_sim 00118 c7 85 c4 09 00 00 01 00 00 00 mov DWORD PTR tv87[rbp], 1 00122 eb 0a jmp SHORT $LN39@sn_get_sim $LN38@sn_get_sim: 00124 c7 85 c4 09 00 00 00 00 00 00 mov DWORD PTR tv87[rbp], 0 $LN39@sn_get_sim: 0012e 8b 85 c4 09 00 00 mov eax, DWORD PTR tv87[rbp] 00134 89 85 d4 00 00 00 mov DWORD PTR is_intel$[rbp], eax ; 104 : const int is_amd = (strcmp(vendor, "AuthenticAMD") == 0); 0013a 48 8d 15 00 00 00 00 lea rdx, OFFSET FLAT:??_C@_0N@FFJGBINN@AuthenticAMD@ 00141 48 8d 8d a8 00 00 00 lea rcx, QWORD PTR vendor$[rbp] 00148 e8 00 00 00 00 call strcmp 0014d 85 c0 test eax, eax 0014f 75 0c jne SHORT $LN40@sn_get_sim 00151 c7 85 c4 09 00 00 01 00 00 00 mov DWORD PTR tv92[rbp], 1 0015b eb 0a jmp SHORT $LN41@sn_get_sim $LN40@sn_get_sim: 0015d c7 85 c4 09 00 00 00 00 00 00 mov DWORD PTR tv92[rbp], 0 $LN41@sn_get_sim: 00167 8b 85 c4 09 00 00 mov eax, DWORD PTR tv92[rbp] 0016d 89 85 f4 00 00 00 mov DWORD PTR is_amd$[rbp], eax ; 105 : const int is_hygon = (strcmp(vendor, "HygonGenuine") == 0); /* 海光: separate from AMD */ 00173 48 8d 15 00 00 00 00 lea rdx, OFFSET FLAT:??_C@_0N@IGLDKOMM@HygonGenuine@ 0017a 48 8d 8d a8 00 00 00 lea rcx, QWORD PTR vendor$[rbp] 00181 e8 00 00 00 00 call strcmp 00186 85 c0 test eax, eax 00188 75 0c jne SHORT $LN42@sn_get_sim 0018a c7 85 c4 09 00 00 01 00 00 00 mov DWORD PTR tv129[rbp], 1 00194 eb 0a jmp SHORT $LN43@sn_get_sim $LN42@sn_get_sim: 00196 c7 85 c4 09 00 00 00 00 00 00 mov DWORD PTR tv129[rbp], 0 $LN43@sn_get_sim: 001a0 8b 85 c4 09 00 00 mov eax, DWORD PTR tv129[rbp] 001a6 89 85 14 01 00 00 mov DWORD PTR is_hygon$[rbp], eax ; 106 : const int is_via = (strcmp(vendor, "CentaurHauls") == 0) || 001ac 48 8d 15 00 00 00 00 lea rdx, OFFSET FLAT:??_C@_0N@DHAFJCOO@CentaurHauls@ 001b3 48 8d 8d a8 00 00 00 lea rcx, QWORD PTR vendor$[rbp] 001ba e8 00 00 00 00 call strcmp 001bf 85 c0 test eax, eax 001c1 74 29 je SHORT $LN44@sn_get_sim 001c3 41 b8 0c 00 00 00 mov r8d, 12 001c9 48 8d 15 00 00 00 00 lea rdx, OFFSET FLAT:??_C@_0N@BDNCIKNF@?5?5Shanghai?5?5@ 001d0 48 8d 8d a8 00 00 00 lea rcx, QWORD PTR vendor$[rbp] 001d7 e8 00 00 00 00 call memcmp 001dc 85 c0 test eax, eax 001de 74 0c je SHORT $LN44@sn_get_sim 001e0 c7 85 c4 09 00 00 00 00 00 00 mov DWORD PTR tv139[rbp], 0 001ea eb 0a jmp SHORT $LN45@sn_get_sim $LN44@sn_get_sim: 001ec c7 85 c4 09 00 00 01 00 00 00 mov DWORD PTR tv139[rbp], 1 $LN45@sn_get_sim: 001f6 8b 85 c4 09 00 00 mov eax, DWORD PTR tv139[rbp] 001fc 89 85 34 01 00 00 mov DWORD PTR is_via$[rbp], eax ; 107 : (memcmp(vendor, " Shanghai ", 12) == 0); /* VIA / Zhaoxin */ ; 108 : ; 109 : /* CPUID.1 */ ; 110 : get_cpuid(1, 0, &eax, &ebx, &ecx, &edx); 00202 48 8d 85 84 00 00 00 lea rax, QWORD PTR edx$[rbp] 00209 48 89 44 24 28 mov QWORD PTR [rsp+40], rax 0020e 48 8d 45 64 lea rax, QWORD PTR ecx$[rbp] 00212 48 89 44 24 20 mov QWORD PTR [rsp+32], rax 00217 4c 8d 4d 44 lea r9, QWORD PTR ebx$[rbp] 0021b 4c 8d 45 24 lea r8, QWORD PTR eax$[rbp] 0021f 33 d2 xor edx, edx 00221 b9 01 00 00 00 mov ecx, 1 00226 e8 00 00 00 00 call get_cpuid 0022b 90 npad 1 ; 111 : int cpuid1_eax = eax; /* saved for Zen1/Zen+ glue-YMM detection */ 0022c 8b 45 24 mov eax, DWORD PTR eax$[rbp] 0022f 89 85 54 01 00 00 mov DWORD PTR cpuid1_eax$[rbp], eax ; 112 : int family = ((eax >> 8) & 0xF) + ((eax >> 20) & 0xFF0); 00235 8b 45 24 mov eax, DWORD PTR eax$[rbp] 00238 c1 f8 08 sar eax, 8 0023b 83 e0 0f and eax, 15 0023e 8b 4d 24 mov ecx, DWORD PTR eax$[rbp] 00241 c1 f9 14 sar ecx, 20 00244 81 e1 f0 0f 00 00 and ecx, 4080 ; 00000ff0H 0024a 03 c1 add eax, ecx 0024c 89 85 74 01 00 00 mov DWORD PTR family$[rbp], eax ; 113 : int model = ((eax >> 4) & 0xF) | ((eax >> 12) & 0xF0); 00252 8b 45 24 mov eax, DWORD PTR eax$[rbp] 00255 c1 f8 04 sar eax, 4 00258 83 e0 0f and eax, 15 0025b 8b 4d 24 mov ecx, DWORD PTR eax$[rbp] 0025e c1 f9 0c sar ecx, 12 00261 81 e1 f0 00 00 00 and ecx, 240 ; 000000f0H 00267 0b c1 or eax, ecx 00269 89 85 94 01 00 00 mov DWORD PTR model$[rbp], eax ; 114 : ; 115 : int has_sse42 = (ecx & (1 << 20)) != 0; 0026f 8b 45 64 mov eax, DWORD PTR ecx$[rbp] 00272 25 00 00 10 00 and eax, 1048576 ; 00100000H 00277 85 c0 test eax, eax 00279 74 0c je SHORT $LN46@sn_get_sim 0027b c7 85 c4 09 00 00 01 00 00 00 mov DWORD PTR tv158[rbp], 1 00285 eb 0a jmp SHORT $LN47@sn_get_sim $LN46@sn_get_sim: 00287 c7 85 c4 09 00 00 00 00 00 00 mov DWORD PTR tv158[rbp], 0 $LN47@sn_get_sim: 00291 8b 85 c4 09 00 00 mov eax, DWORD PTR tv158[rbp] 00297 89 85 b4 01 00 00 mov DWORD PTR has_sse42$[rbp], eax ; 116 : int has_avx = (ecx & (1 << 28)) != 0; 0029d 8b 45 64 mov eax, DWORD PTR ecx$[rbp] 002a0 25 00 00 00 10 and eax, 268435456 ; 10000000H 002a5 85 c0 test eax, eax 002a7 74 0c je SHORT $LN48@sn_get_sim 002a9 c7 85 c4 09 00 00 01 00 00 00 mov DWORD PTR tv161[rbp], 1 002b3 eb 0a jmp SHORT $LN49@sn_get_sim $LN48@sn_get_sim: 002b5 c7 85 c4 09 00 00 00 00 00 00 mov DWORD PTR tv161[rbp], 0 $LN49@sn_get_sim: 002bf 8b 85 c4 09 00 00 mov eax, DWORD PTR tv161[rbp] 002c5 89 85 d4 01 00 00 mov DWORD PTR has_avx$[rbp], eax ; 117 : int has_osxsave = (ecx & (1 << 27)) != 0; 002cb 8b 45 64 mov eax, DWORD PTR ecx$[rbp] 002ce 25 00 00 00 08 and eax, 134217728 ; 08000000H 002d3 85 c0 test eax, eax 002d5 74 0c je SHORT $LN50@sn_get_sim 002d7 c7 85 c4 09 00 00 01 00 00 00 mov DWORD PTR tv164[rbp], 1 002e1 eb 0a jmp SHORT $LN51@sn_get_sim $LN50@sn_get_sim: 002e3 c7 85 c4 09 00 00 00 00 00 00 mov DWORD PTR tv164[rbp], 0 $LN51@sn_get_sim: 002ed 8b 85 c4 09 00 00 mov eax, DWORD PTR tv164[rbp] 002f3 89 85 f4 01 00 00 mov DWORD PTR has_osxsave$[rbp], eax ; 118 : int has_fma = (ecx & (1 << 12)) != 0; 002f9 8b 45 64 mov eax, DWORD PTR ecx$[rbp] 002fc 25 00 10 00 00 and eax, 4096 ; 00001000H 00301 85 c0 test eax, eax 00303 74 0c je SHORT $LN52@sn_get_sim 00305 c7 85 c4 09 00 00 01 00 00 00 mov DWORD PTR tv167[rbp], 1 0030f eb 0a jmp SHORT $LN53@sn_get_sim $LN52@sn_get_sim: 00311 c7 85 c4 09 00 00 00 00 00 00 mov DWORD PTR tv167[rbp], 0 $LN53@sn_get_sim: 0031b 8b 85 c4 09 00 00 mov eax, DWORD PTR tv167[rbp] 00321 89 85 14 02 00 00 mov DWORD PTR has_fma$[rbp], eax ; 119 : int has_f16c = (ecx & (1 << 29)) != 0; 00327 8b 45 64 mov eax, DWORD PTR ecx$[rbp] 0032a 25 00 00 00 20 and eax, 536870912 ; 20000000H 0032f 85 c0 test eax, eax 00331 74 0c je SHORT $LN54@sn_get_sim 00333 c7 85 c4 09 00 00 01 00 00 00 mov DWORD PTR tv170[rbp], 1 0033d eb 0a jmp SHORT $LN55@sn_get_sim $LN54@sn_get_sim: 0033f c7 85 c4 09 00 00 00 00 00 00 mov DWORD PTR tv170[rbp], 0 $LN55@sn_get_sim: 00349 8b 85 c4 09 00 00 mov eax, DWORD PTR tv170[rbp] 0034f 89 85 34 02 00 00 mov DWORD PTR has_f16c$[rbp], eax ; 120 : ; 121 : uint64_t root = SIMDID_PACK_ROOT(SIMDID_ROOT_X86_64); 00355 48 c7 85 58 02 00 00 01 00 00 00 mov QWORD PTR root$[rbp], 1 ; 122 : uint64_t manu = SIMDID_PACK_MANU(is_intel ? SIMDID_MANU_INTEL : 00360 83 bd d4 00 00 00 00 cmp DWORD PTR is_intel$[rbp], 0 00367 74 0c je SHORT $LN62@sn_get_sim 00369 c7 85 c4 09 00 00 01 00 00 00 mov DWORD PTR tv178[rbp], 1 00373 eb 6d jmp SHORT $LN63@sn_get_sim $LN62@sn_get_sim: 00375 83 bd f4 00 00 00 00 cmp DWORD PTR is_amd$[rbp], 0 0037c 74 0c je SHORT $LN60@sn_get_sim 0037e c7 85 c8 09 00 00 02 00 00 00 mov DWORD PTR tv176[rbp], 2 00388 eb 4c jmp SHORT $LN61@sn_get_sim $LN60@sn_get_sim: 0038a 83 bd 14 01 00 00 00 cmp DWORD PTR is_hygon$[rbp], 0 00391 74 0c je SHORT $LN58@sn_get_sim 00393 c7 85 cc 09 00 00 04 00 00 00 mov DWORD PTR tv174[rbp], 4 0039d eb 2b jmp SHORT $LN59@sn_get_sim $LN58@sn_get_sim: 0039f 83 bd 34 01 00 00 00 cmp DWORD PTR is_via$[rbp], 0 003a6 74 0c je SHORT $LN56@sn_get_sim 003a8 c7 85 d0 09 00 00 03 00 00 00 mov DWORD PTR tv172[rbp], 3 003b2 eb 0a jmp SHORT $LN57@sn_get_sim $LN56@sn_get_sim: 003b4 c7 85 d0 09 00 00 00 00 00 00 mov DWORD PTR tv172[rbp], 0 $LN57@sn_get_sim: 003be 8b 85 d0 09 00 00 mov eax, DWORD PTR tv172[rbp] 003c4 89 85 cc 09 00 00 mov DWORD PTR tv174[rbp], eax $LN59@sn_get_sim: 003ca 8b 85 cc 09 00 00 mov eax, DWORD PTR tv174[rbp] 003d0 89 85 c8 09 00 00 mov DWORD PTR tv176[rbp], eax $LN61@sn_get_sim: 003d6 8b 85 c8 09 00 00 mov eax, DWORD PTR tv176[rbp] 003dc 89 85 c4 09 00 00 mov DWORD PTR tv178[rbp], eax $LN63@sn_get_sim: 003e2 48 63 85 c4 09 00 00 movsxd rax, DWORD PTR tv178[rbp] 003e9 48 83 e0 0f and rax, 15 003ed 48 c1 e0 04 shl rax, 4 003f1 48 89 85 78 02 00 00 mov QWORD PTR manu$[rbp], rax ; 123 : is_amd ? SIMDID_MANU_AMD : ; 124 : is_hygon ? SIMDID_MANU_HYGON : ; 125 : is_via ? SIMDID_MANU_VIA : ; 126 : SIMDID_MANU_UNKNOWN); ; 127 : uint64_t main_lvl = SIMDID_PACK_MAIN(SIMDID_MAIN_LVL_NONE); 003f8 48 c7 85 98 02 00 00 00 00 00 00 mov QWORD PTR main_lvl$[rbp], 0 ; 128 : uint64_t avx512_bits = 0; 00403 48 c7 85 b8 02 00 00 00 00 00 00 mov QWORD PTR avx512_bits$[rbp], 0 ; 129 : uint64_t amx_bits = 0; 0040e 48 c7 85 d8 02 00 00 00 00 00 00 mov QWORD PTR amx_bits$[rbp], 0 ; 130 : uint64_t avx_bits = 0; 00419 48 c7 85 f8 02 00 00 00 00 00 00 mov QWORD PTR avx_bits$[rbp], 0 ; 131 : uint64_t avx10_bits = 0; 00424 48 c7 85 18 03 00 00 00 00 00 00 mov QWORD PTR avx10_bits$[rbp], 0 ; 132 : int has_hybrid = 0; /* filled from CPUID.7.0 EDX[15] when AVX present */ 0042f c7 85 34 03 00 00 00 00 00 00 mov DWORD PTR has_hybrid$[rbp], 0 ; 133 : ; 134 : /* Baseline main level */ ; 135 : if (has_sse42) 00439 83 bd b4 01 00 00 00 cmp DWORD PTR has_sse42$[rbp], 0 00440 74 0b je SHORT $LN2@sn_get_sim ; 136 : main_lvl = SIMDID_PACK_MAIN(SIMDID_MAIN_LVL_SSE); 00442 48 c7 85 98 02 00 00 00 01 00 00 mov QWORD PTR main_lvl$[rbp], 256 ; 00000100H $LN2@sn_get_sim: ; 137 : ; 138 : if (has_avx && has_osxsave && xgetbv_has_xmm_ymm()) { 0044d 83 bd d4 01 00 00 00 cmp DWORD PTR has_avx$[rbp], 0 00454 0f 84 af 06 00 00 je $LN3@sn_get_sim 0045a 83 bd f4 01 00 00 00 cmp DWORD PTR has_osxsave$[rbp], 0 00461 0f 84 a2 06 00 00 je $LN3@sn_get_sim 00467 e8 00 00 00 00 call xgetbv_has_xmm_ymm 0046c 85 c0 test eax, eax 0046e 0f 84 95 06 00 00 je $LN3@sn_get_sim ; 139 : avx_bits |= SIMDID_AVX; 00474 48 8b 85 f8 02 00 00 mov rax, QWORD PTR avx_bits$[rbp] 0047b 48 83 c8 01 or rax, 1 0047f 48 89 85 f8 02 00 00 mov QWORD PTR avx_bits$[rbp], rax ; 140 : ; 141 : /* Glued/split-lane YMM: early AMD Zen1/Zen+, Hygon, and VIA/Zhaoxin */ ; 142 : if (is_amd_glue_ymm(vendor, cpuid1_eax) || is_via) 00486 8b 95 54 01 00 00 mov edx, DWORD PTR cpuid1_eax$[rbp] 0048c 48 8d 8d a8 00 00 00 lea rcx, QWORD PTR vendor$[rbp] 00493 e8 00 00 00 00 call is_amd_glue_ymm 00498 85 c0 test eax, eax 0049a 75 09 jne SHORT $LN5@sn_get_sim 0049c 83 bd 34 01 00 00 00 cmp DWORD PTR is_via$[rbp], 0 004a3 74 12 je SHORT $LN4@sn_get_sim $LN5@sn_get_sim: ; 143 : avx_bits |= SIMDID_AVX_DUAL; 004a5 48 8b 85 f8 02 00 00 mov rax, QWORD PTR avx_bits$[rbp] 004ac 48 83 c8 10 or rax, 16 004b0 48 89 85 f8 02 00 00 mov QWORD PTR avx_bits$[rbp], rax $LN4@sn_get_sim: ; 144 : ; 145 : /* CPUID.7.0 */ ; 146 : get_cpuid(7, 0, &eax, &ebx, &ecx, &edx); 004b7 48 8d 85 84 00 00 00 lea rax, QWORD PTR edx$[rbp] 004be 48 89 44 24 28 mov QWORD PTR [rsp+40], rax 004c3 48 8d 45 64 lea rax, QWORD PTR ecx$[rbp] 004c7 48 89 44 24 20 mov QWORD PTR [rsp+32], rax 004cc 4c 8d 4d 44 lea r9, QWORD PTR ebx$[rbp] 004d0 4c 8d 45 24 lea r8, QWORD PTR eax$[rbp] 004d4 33 d2 xor edx, edx 004d6 b9 07 00 00 00 mov ecx, 7 004db e8 00 00 00 00 call get_cpuid 004e0 90 npad 1 ; 147 : const int has_bmi1 = (ebx & (1 << 3)) != 0; 004e1 8b 45 44 mov eax, DWORD PTR ebx$[rbp] 004e4 83 e0 08 and eax, 8 004e7 85 c0 test eax, eax 004e9 74 0c je SHORT $LN64@sn_get_sim 004eb c7 85 c4 09 00 00 01 00 00 00 mov DWORD PTR tv202[rbp], 1 004f5 eb 0a jmp SHORT $LN65@sn_get_sim $LN64@sn_get_sim: 004f7 c7 85 c4 09 00 00 00 00 00 00 mov DWORD PTR tv202[rbp], 0 $LN65@sn_get_sim: 00501 8b 85 c4 09 00 00 mov eax, DWORD PTR tv202[rbp] 00507 89 85 54 03 00 00 mov DWORD PTR has_bmi1$17[rbp], eax ; 148 : const int has_bmi2 = (ebx & (1 << 8)) != 0; 0050d 8b 45 44 mov eax, DWORD PTR ebx$[rbp] 00510 25 00 01 00 00 and eax, 256 ; 00000100H 00515 85 c0 test eax, eax 00517 74 0c je SHORT $LN66@sn_get_sim 00519 c7 85 c4 09 00 00 01 00 00 00 mov DWORD PTR tv205[rbp], 1 00523 eb 0a jmp SHORT $LN67@sn_get_sim $LN66@sn_get_sim: 00525 c7 85 c4 09 00 00 00 00 00 00 mov DWORD PTR tv205[rbp], 0 $LN67@sn_get_sim: 0052f 8b 85 c4 09 00 00 mov eax, DWORD PTR tv205[rbp] 00535 89 85 74 03 00 00 mov DWORD PTR has_bmi2$18[rbp], eax ; 149 : const int has_avx2 = (ebx & (1 << 5)) != 0; 0053b 8b 45 44 mov eax, DWORD PTR ebx$[rbp] 0053e 83 e0 20 and eax, 32 ; 00000020H 00541 85 c0 test eax, eax 00543 74 0c je SHORT $LN68@sn_get_sim 00545 c7 85 c4 09 00 00 01 00 00 00 mov DWORD PTR tv208[rbp], 1 0054f eb 0a jmp SHORT $LN69@sn_get_sim $LN68@sn_get_sim: 00551 c7 85 c4 09 00 00 00 00 00 00 mov DWORD PTR tv208[rbp], 0 $LN69@sn_get_sim: 0055b 8b 85 c4 09 00 00 mov eax, DWORD PTR tv208[rbp] 00561 89 85 94 03 00 00 mov DWORD PTR has_avx2$19[rbp], eax ; 150 : const int has_avx512f = (ebx & (1 << 16)) != 0; 00567 8b 45 44 mov eax, DWORD PTR ebx$[rbp] 0056a 25 00 00 01 00 and eax, 65536 ; 00010000H 0056f 85 c0 test eax, eax 00571 74 0c je SHORT $LN70@sn_get_sim 00573 c7 85 c4 09 00 00 01 00 00 00 mov DWORD PTR tv211[rbp], 1 0057d eb 0a jmp SHORT $LN71@sn_get_sim $LN70@sn_get_sim: 0057f c7 85 c4 09 00 00 00 00 00 00 mov DWORD PTR tv211[rbp], 0 $LN71@sn_get_sim: 00589 8b 85 c4 09 00 00 mov eax, DWORD PTR tv211[rbp] 0058f 89 85 b4 03 00 00 mov DWORD PTR has_avx512f$20[rbp], eax ; 151 : const int has_avx512dq = (ebx & (1 << 17)) != 0; 00595 8b 45 44 mov eax, DWORD PTR ebx$[rbp] 00598 25 00 00 02 00 and eax, 131072 ; 00020000H 0059d 85 c0 test eax, eax 0059f 74 0c je SHORT $LN72@sn_get_sim 005a1 c7 85 c4 09 00 00 01 00 00 00 mov DWORD PTR tv214[rbp], 1 005ab eb 0a jmp SHORT $LN73@sn_get_sim $LN72@sn_get_sim: 005ad c7 85 c4 09 00 00 00 00 00 00 mov DWORD PTR tv214[rbp], 0 $LN73@sn_get_sim: 005b7 8b 85 c4 09 00 00 mov eax, DWORD PTR tv214[rbp] 005bd 89 85 d4 03 00 00 mov DWORD PTR has_avx512dq$21[rbp], eax ; 152 : const int has_avx512bw = (ebx & (1 << 30)) != 0; 005c3 8b 45 44 mov eax, DWORD PTR ebx$[rbp] 005c6 25 00 00 00 40 and eax, 1073741824 ; 40000000H 005cb 85 c0 test eax, eax 005cd 74 0c je SHORT $LN74@sn_get_sim 005cf c7 85 c4 09 00 00 01 00 00 00 mov DWORD PTR tv217[rbp], 1 005d9 eb 0a jmp SHORT $LN75@sn_get_sim $LN74@sn_get_sim: 005db c7 85 c4 09 00 00 00 00 00 00 mov DWORD PTR tv217[rbp], 0 $LN75@sn_get_sim: 005e5 8b 85 c4 09 00 00 mov eax, DWORD PTR tv217[rbp] 005eb 89 85 f4 03 00 00 mov DWORD PTR has_avx512bw$22[rbp], eax ; 153 : const int has_avx512vl = (ebx & (1u << 31)) != 0; 005f1 8b 45 44 mov eax, DWORD PTR ebx$[rbp] 005f4 25 00 00 00 80 and eax, -2147483648 ; 80000000H 005f9 85 c0 test eax, eax 005fb 74 0c je SHORT $LN76@sn_get_sim 005fd c7 85 c4 09 00 00 01 00 00 00 mov DWORD PTR tv220[rbp], 1 00607 eb 0a jmp SHORT $LN77@sn_get_sim $LN76@sn_get_sim: 00609 c7 85 c4 09 00 00 00 00 00 00 mov DWORD PTR tv220[rbp], 0 $LN77@sn_get_sim: 00613 8b 85 c4 09 00 00 mov eax, DWORD PTR tv220[rbp] 00619 89 85 14 04 00 00 mov DWORD PTR has_avx512vl$23[rbp], eax ; 154 : const int has_avx512_vnni = (ebx & (1 << 11)) != 0; 0061f 8b 45 44 mov eax, DWORD PTR ebx$[rbp] 00622 25 00 08 00 00 and eax, 2048 ; 00000800H 00627 85 c0 test eax, eax 00629 74 0c je SHORT $LN78@sn_get_sim 0062b c7 85 c4 09 00 00 01 00 00 00 mov DWORD PTR tv223[rbp], 1 00635 eb 0a jmp SHORT $LN79@sn_get_sim $LN78@sn_get_sim: 00637 c7 85 c4 09 00 00 00 00 00 00 mov DWORD PTR tv223[rbp], 0 $LN79@sn_get_sim: 00641 8b 85 c4 09 00 00 mov eax, DWORD PTR tv223[rbp] 00647 89 85 34 04 00 00 mov DWORD PTR has_avx512_vnni$24[rbp], eax ; 155 : const int has_vbmi = (ecx & (1 << 1)) != 0; 0064d 8b 45 64 mov eax, DWORD PTR ecx$[rbp] 00650 83 e0 02 and eax, 2 00653 85 c0 test eax, eax 00655 74 0c je SHORT $LN80@sn_get_sim 00657 c7 85 c4 09 00 00 01 00 00 00 mov DWORD PTR tv258[rbp], 1 00661 eb 0a jmp SHORT $LN81@sn_get_sim $LN80@sn_get_sim: 00663 c7 85 c4 09 00 00 00 00 00 00 mov DWORD PTR tv258[rbp], 0 $LN81@sn_get_sim: 0066d 8b 85 c4 09 00 00 mov eax, DWORD PTR tv258[rbp] 00673 89 85 54 04 00 00 mov DWORD PTR has_vbmi$25[rbp], eax ; 156 : const int has_vbmi2 = (ecx & (1 << 6)) != 0; 00679 8b 45 64 mov eax, DWORD PTR ecx$[rbp] 0067c 83 e0 40 and eax, 64 ; 00000040H 0067f 85 c0 test eax, eax 00681 74 0c je SHORT $LN82@sn_get_sim 00683 c7 85 c4 09 00 00 01 00 00 00 mov DWORD PTR tv261[rbp], 1 0068d eb 0a jmp SHORT $LN83@sn_get_sim $LN82@sn_get_sim: 0068f c7 85 c4 09 00 00 00 00 00 00 mov DWORD PTR tv261[rbp], 0 $LN83@sn_get_sim: 00699 8b 85 c4 09 00 00 mov eax, DWORD PTR tv261[rbp] 0069f 89 85 74 04 00 00 mov DWORD PTR has_vbmi2$26[rbp], eax ; 157 : ; 158 : /* AMX in leaf 7 subleaf 0 EDX bits 24/25/26 — capture before ; 159 : overwriting regs with subleaf 1 */ ; 160 : const int has_amx_tile = (edx & (1 << 24)) != 0; 006a5 8b 85 84 00 00 00 mov eax, DWORD PTR edx$[rbp] 006ab 25 00 00 00 01 and eax, 16777216 ; 01000000H 006b0 85 c0 test eax, eax 006b2 74 0c je SHORT $LN84@sn_get_sim 006b4 c7 85 c4 09 00 00 01 00 00 00 mov DWORD PTR tv264[rbp], 1 006be eb 0a jmp SHORT $LN85@sn_get_sim $LN84@sn_get_sim: 006c0 c7 85 c4 09 00 00 00 00 00 00 mov DWORD PTR tv264[rbp], 0 $LN85@sn_get_sim: 006ca 8b 85 c4 09 00 00 mov eax, DWORD PTR tv264[rbp] 006d0 89 85 94 04 00 00 mov DWORD PTR has_amx_tile$27[rbp], eax ; 161 : const int has_amx_int8 = (edx & (1 << 25)) != 0; 006d6 8b 85 84 00 00 00 mov eax, DWORD PTR edx$[rbp] 006dc 25 00 00 00 02 and eax, 33554432 ; 02000000H 006e1 85 c0 test eax, eax 006e3 74 0c je SHORT $LN86@sn_get_sim 006e5 c7 85 c4 09 00 00 01 00 00 00 mov DWORD PTR tv267[rbp], 1 006ef eb 0a jmp SHORT $LN87@sn_get_sim $LN86@sn_get_sim: 006f1 c7 85 c4 09 00 00 00 00 00 00 mov DWORD PTR tv267[rbp], 0 $LN87@sn_get_sim: 006fb 8b 85 c4 09 00 00 mov eax, DWORD PTR tv267[rbp] 00701 89 85 b4 04 00 00 mov DWORD PTR has_amx_int8$28[rbp], eax ; 162 : const int has_amx_bf16 = (edx & (1 << 22)) != 0; 00707 8b 85 84 00 00 00 mov eax, DWORD PTR edx$[rbp] 0070d 25 00 00 40 00 and eax, 4194304 ; 00400000H 00712 85 c0 test eax, eax 00714 74 0c je SHORT $LN88@sn_get_sim 00716 c7 85 c4 09 00 00 01 00 00 00 mov DWORD PTR tv270[rbp], 1 00720 eb 0a jmp SHORT $LN89@sn_get_sim $LN88@sn_get_sim: 00722 c7 85 c4 09 00 00 00 00 00 00 mov DWORD PTR tv270[rbp], 0 $LN89@sn_get_sim: 0072c 8b 85 c4 09 00 00 mov eax, DWORD PTR tv270[rbp] 00732 89 85 d4 04 00 00 mov DWORD PTR has_amx_bf16$29[rbp], eax ; 163 : has_hybrid = (edx & (1 << 15)) != 0; /* Intel hybrid core topology */ 00738 8b 85 84 00 00 00 mov eax, DWORD PTR edx$[rbp] 0073e 25 00 80 00 00 and eax, 32768 ; 00008000H 00743 85 c0 test eax, eax 00745 74 0c je SHORT $LN90@sn_get_sim 00747 c7 85 c4 09 00 00 01 00 00 00 mov DWORD PTR tv273[rbp], 1 00751 eb 0a jmp SHORT $LN91@sn_get_sim $LN90@sn_get_sim: 00753 c7 85 c4 09 00 00 00 00 00 00 mov DWORD PTR tv273[rbp], 0 $LN91@sn_get_sim: 0075d 8b 85 c4 09 00 00 mov eax, DWORD PTR tv273[rbp] 00763 89 85 34 03 00 00 mov DWORD PTR has_hybrid$[rbp], eax ; 164 : ; 165 : /* leaf 7, subleaf 1 for BF16/FP16/AVX10 convergence */ ; 166 : get_cpuid(7, 1, &eax, &ebx, &ecx, &edx); 00769 48 8d 85 84 00 00 00 lea rax, QWORD PTR edx$[rbp] 00770 48 89 44 24 28 mov QWORD PTR [rsp+40], rax 00775 48 8d 45 64 lea rax, QWORD PTR ecx$[rbp] 00779 48 89 44 24 20 mov QWORD PTR [rsp+32], rax 0077e 4c 8d 4d 44 lea r9, QWORD PTR ebx$[rbp] 00782 4c 8d 45 24 lea r8, QWORD PTR eax$[rbp] 00786 ba 01 00 00 00 mov edx, 1 0078b b9 07 00 00 00 mov ecx, 7 00790 e8 00 00 00 00 call get_cpuid 00795 90 npad 1 ; 167 : const int has_bf16 = (eax & (1 << 5)) != 0; /* AVX512_BF16 */ 00796 8b 45 24 mov eax, DWORD PTR eax$[rbp] 00799 83 e0 20 and eax, 32 ; 00000020H 0079c 85 c0 test eax, eax 0079e 74 0c je SHORT $LN92@sn_get_sim 007a0 c7 85 c4 09 00 00 01 00 00 00 mov DWORD PTR tv282[rbp], 1 007aa eb 0a jmp SHORT $LN93@sn_get_sim $LN92@sn_get_sim: 007ac c7 85 c4 09 00 00 00 00 00 00 mov DWORD PTR tv282[rbp], 0 $LN93@sn_get_sim: 007b6 8b 85 c4 09 00 00 mov eax, DWORD PTR tv282[rbp] 007bc 89 85 f4 04 00 00 mov DWORD PTR has_bf16$30[rbp], eax ; 168 : const int has_fp16 = (eax & (1 << 23)) != 0; /* AVX512_FP16 */ 007c2 8b 45 24 mov eax, DWORD PTR eax$[rbp] 007c5 25 00 00 80 00 and eax, 8388608 ; 00800000H 007ca 85 c0 test eax, eax 007cc 74 0c je SHORT $LN94@sn_get_sim 007ce c7 85 c4 09 00 00 01 00 00 00 mov DWORD PTR tv285[rbp], 1 007d8 eb 0a jmp SHORT $LN95@sn_get_sim $LN94@sn_get_sim: 007da c7 85 c4 09 00 00 00 00 00 00 mov DWORD PTR tv285[rbp], 0 $LN95@sn_get_sim: 007e4 8b 85 c4 09 00 00 mov eax, DWORD PTR tv285[rbp] 007ea 89 85 14 05 00 00 mov DWORD PTR has_fp16$31[rbp], eax ; 169 : const int has_avx10 = (edx & (1 << 19)) != 0; /* AVX10 convergence */ 007f0 8b 85 84 00 00 00 mov eax, DWORD PTR edx$[rbp] 007f6 25 00 00 08 00 and eax, 524288 ; 00080000H 007fb 85 c0 test eax, eax 007fd 74 0c je SHORT $LN96@sn_get_sim 007ff c7 85 c4 09 00 00 01 00 00 00 mov DWORD PTR tv288[rbp], 1 00809 eb 0a jmp SHORT $LN97@sn_get_sim $LN96@sn_get_sim: 0080b c7 85 c4 09 00 00 00 00 00 00 mov DWORD PTR tv288[rbp], 0 $LN97@sn_get_sim: 00815 8b 85 c4 09 00 00 mov eax, DWORD PTR tv288[rbp] 0081b 89 85 34 05 00 00 mov DWORD PTR has_avx10$32[rbp], eax ; 170 : ; 171 : if (has_avx2) { 00821 83 bd 94 03 00 00 00 cmp DWORD PTR has_avx2$19[rbp], 0 00828 74 53 je SHORT $LN6@sn_get_sim ; 172 : avx_bits |= SIMDID_AVX2; 0082a 48 8b 85 f8 02 00 00 mov rax, QWORD PTR avx_bits$[rbp] 00831 48 83 c8 02 or rax, 2 00835 48 89 85 f8 02 00 00 mov QWORD PTR avx_bits$[rbp], rax ; 173 : if (has_fma) 0083c 83 bd 14 02 00 00 00 cmp DWORD PTR has_fma$[rbp], 0 00843 74 12 je SHORT $LN7@sn_get_sim ; 174 : avx_bits |= SIMDID_AVX_FMA; 00845 48 8b 85 f8 02 00 00 mov rax, QWORD PTR avx_bits$[rbp] 0084c 48 83 c8 04 or rax, 4 00850 48 89 85 f8 02 00 00 mov QWORD PTR avx_bits$[rbp], rax $LN7@sn_get_sim: ; 175 : if (has_f16c) 00857 83 bd 34 02 00 00 00 cmp DWORD PTR has_f16c$[rbp], 0 0085e 74 12 je SHORT $LN8@sn_get_sim ; 176 : avx_bits |= SIMDID_AVX_F16C; 00860 48 8b 85 f8 02 00 00 mov rax, QWORD PTR avx_bits$[rbp] 00867 48 83 c8 08 or rax, 8 0086b 48 89 85 f8 02 00 00 mov QWORD PTR avx_bits$[rbp], rax $LN8@sn_get_sim: ; 177 : ; 178 : main_lvl = SIMDID_PACK_MAIN(SIMDID_MAIN_LVL_AVX2); 00872 48 c7 85 98 02 00 00 00 02 00 00 mov QWORD PTR main_lvl$[rbp], 512 ; 00000200H $LN6@sn_get_sim: ; 179 : } ; 180 : ; 181 : if (has_avx512f && xgetbv_has_avx512_state()) { 0087d 83 bd b4 03 00 00 00 cmp DWORD PTR has_avx512f$20[rbp], 0 00884 0f 84 7f 02 00 00 je $LN9@sn_get_sim 0088a e8 00 00 00 00 call xgetbv_has_avx512_state 0088f 85 c0 test eax, eax 00891 0f 84 72 02 00 00 je $LN9@sn_get_sim ; 182 : /* Ensure base subset present */ ; 183 : if (has_avx512bw && has_avx512vl && has_avx512dq) { 00897 83 bd f4 03 00 00 00 cmp DWORD PTR has_avx512bw$22[rbp], 0 0089e 74 24 je SHORT $LN10@sn_get_sim 008a0 83 bd 14 04 00 00 00 cmp DWORD PTR has_avx512vl$23[rbp], 0 008a7 74 1b je SHORT $LN10@sn_get_sim 008a9 83 bd d4 03 00 00 00 cmp DWORD PTR has_avx512dq$21[rbp], 0 008b0 74 12 je SHORT $LN10@sn_get_sim ; 184 : avx512_bits |= SIMDID_AVX512_BASE; 008b2 48 8b 85 b8 02 00 00 mov rax, QWORD PTR avx512_bits$[rbp] 008b9 48 83 c8 10 or rax, 16 008bd 48 89 85 b8 02 00 00 mov QWORD PTR avx512_bits$[rbp], rax $LN10@sn_get_sim: ; 185 : } ; 186 : if (has_avx512_vnni) 008c4 83 bd 34 04 00 00 00 cmp DWORD PTR has_avx512_vnni$24[rbp], 0 008cb 74 13 je SHORT $LN11@sn_get_sim ; 187 : avx512_bits |= SIMDID_AVX512_VNNI; 008cd 48 8b 85 b8 02 00 00 mov rax, QWORD PTR avx512_bits$[rbp] 008d4 48 0f ba e8 0b bts rax, 11 008d9 48 89 85 b8 02 00 00 mov QWORD PTR avx512_bits$[rbp], rax $LN11@sn_get_sim: ; 188 : if (has_bf16) 008e0 83 bd f4 04 00 00 00 cmp DWORD PTR has_bf16$30[rbp], 0 008e7 74 13 je SHORT $LN12@sn_get_sim ; 189 : avx512_bits |= SIMDID_AVX512_BF16; 008e9 48 8b 85 b8 02 00 00 mov rax, QWORD PTR avx512_bits$[rbp] 008f0 48 0f ba e8 0c bts rax, 12 008f5 48 89 85 b8 02 00 00 mov QWORD PTR avx512_bits$[rbp], rax $LN12@sn_get_sim: ; 190 : if (has_fp16) 008fc 83 bd 14 05 00 00 00 cmp DWORD PTR has_fp16$31[rbp], 0 00903 74 13 je SHORT $LN13@sn_get_sim ; 191 : avx512_bits |= SIMDID_AVX512_FP16; 00905 48 8b 85 b8 02 00 00 mov rax, QWORD PTR avx512_bits$[rbp] 0090c 48 0f ba e8 0d bts rax, 13 00911 48 89 85 b8 02 00 00 mov QWORD PTR avx512_bits$[rbp], rax $LN13@sn_get_sim: ; 192 : if (has_vbmi) 00918 83 bd 54 04 00 00 00 cmp DWORD PTR has_vbmi$25[rbp], 0 0091f 74 13 je SHORT $LN14@sn_get_sim ; 193 : avx512_bits |= SIMDID_AVX512_VBMI; 00921 48 8b 85 b8 02 00 00 mov rax, QWORD PTR avx512_bits$[rbp] 00928 48 0f ba e8 09 bts rax, 9 0092d 48 89 85 b8 02 00 00 mov QWORD PTR avx512_bits$[rbp], rax $LN14@sn_get_sim: ; 194 : if (has_vbmi2) 00934 83 bd 74 04 00 00 00 cmp DWORD PTR has_vbmi2$26[rbp], 0 0093b 74 13 je SHORT $LN15@sn_get_sim ; 195 : avx512_bits |= SIMDID_AVX512_VBMI2; 0093d 48 8b 85 b8 02 00 00 mov rax, QWORD PTR avx512_bits$[rbp] 00944 48 0f ba e8 0a bts rax, 10 00949 48 89 85 b8 02 00 00 mov QWORD PTR avx512_bits$[rbp], rax $LN15@sn_get_sim: ; 196 : ; 197 : /* Execution-width classification: ; 198 : * Intel all → NATIVE (genuine 512-bit ALU; SKX dual-port is native) ; 199 : * AMD Zen4 → DUAL (dual-pump 256-bit, Family 0x19) ; 200 : * AMD Zen5+ → NATIVE (native 512-bit, Family >= 0x1A) ; 201 : * Hygon/VIA/unknown → UNKNOWN (conservative) */ ; 202 : if (is_intel) 00950 83 bd d4 00 00 00 00 cmp DWORD PTR is_intel$[rbp], 0 00957 74 15 je SHORT $LN16@sn_get_sim ; 203 : avx512_bits |= SIMDID_AVX512_IMPL_NATIVE; 00959 48 8b 85 b8 02 00 00 mov rax, QWORD PTR avx512_bits$[rbp] 00960 48 0f ba e8 07 bts rax, 7 00965 48 89 85 b8 02 00 00 mov QWORD PTR avx512_bits$[rbp], rax 0096c eb 38 jmp SHORT $LN17@sn_get_sim $LN16@sn_get_sim: ; 204 : else if (is_amd) 0096e 83 bd f4 00 00 00 00 cmp DWORD PTR is_amd$[rbp], 0 00975 74 21 je SHORT $LN18@sn_get_sim ; 205 : avx512_bits |= amd_avx512_impl(family); 00977 8b 8d 74 01 00 00 mov ecx, DWORD PTR family$[rbp] 0097d e8 00 00 00 00 call amd_avx512_impl 00982 48 8b 8d b8 02 00 00 mov rcx, QWORD PTR avx512_bits$[rbp] 00989 48 0b c8 or rcx, rax 0098c 48 8b c1 mov rax, rcx 0098f 48 89 85 b8 02 00 00 mov QWORD PTR avx512_bits$[rbp], rax 00996 eb 0e jmp SHORT $LN19@sn_get_sim $LN18@sn_get_sim: ; 206 : else ; 207 : avx512_bits |= SIMDID_AVX512_IMPL_UNKNOWN; 00998 48 8b 85 b8 02 00 00 mov rax, QWORD PTR avx512_bits$[rbp] 0099f 48 89 85 b8 02 00 00 mov QWORD PTR avx512_bits$[rbp], rax $LN19@sn_get_sim: $LN17@sn_get_sim: ; 208 : ; 209 : /* main level for AVX512 */ ; 210 : main_lvl = SIMDID_PACK_MAIN(SIMDID_MAIN_LVL_AVX512); 009a6 48 c7 85 98 02 00 00 00 03 00 00 mov QWORD PTR main_lvl$[rbp], 768 ; 00000300H ; 211 : ; 212 : /* AMX promotion if present */ ; 213 : if (has_amx_tile) { 009b1 83 bd 94 04 00 00 00 cmp DWORD PTR has_amx_tile$27[rbp], 0 009b8 74 53 je SHORT $LN20@sn_get_sim ; 214 : amx_bits |= SIMDID_AMX_TILE; 009ba 48 8b 85 d8 02 00 00 mov rax, QWORD PTR amx_bits$[rbp] 009c1 48 83 c8 01 or rax, 1 009c5 48 89 85 d8 02 00 00 mov QWORD PTR amx_bits$[rbp], rax ; 215 : if (has_amx_int8) 009cc 83 bd b4 04 00 00 00 cmp DWORD PTR has_amx_int8$28[rbp], 0 009d3 74 12 je SHORT $LN21@sn_get_sim ; 216 : amx_bits |= SIMDID_AMX_INT8; 009d5 48 8b 85 d8 02 00 00 mov rax, QWORD PTR amx_bits$[rbp] 009dc 48 83 c8 02 or rax, 2 009e0 48 89 85 d8 02 00 00 mov QWORD PTR amx_bits$[rbp], rax $LN21@sn_get_sim: ; 217 : if (has_amx_bf16) 009e7 83 bd d4 04 00 00 00 cmp DWORD PTR has_amx_bf16$29[rbp], 0 009ee 74 12 je SHORT $LN22@sn_get_sim ; 218 : amx_bits |= SIMDID_AMX_BF16; 009f0 48 8b 85 d8 02 00 00 mov rax, QWORD PTR amx_bits$[rbp] 009f7 48 83 c8 04 or rax, 4 009fb 48 89 85 d8 02 00 00 mov QWORD PTR amx_bits$[rbp], rax $LN22@sn_get_sim: ; 219 : main_lvl = SIMDID_PACK_MAIN(SIMDID_MAIN_LVL_AMX); 00a02 48 c7 85 98 02 00 00 00 04 00 00 mov QWORD PTR main_lvl$[rbp], 1024 ; 00000400H $LN20@sn_get_sim: ; 220 : } ; 221 : ; 222 : /* AVX10 detection — requires AVX10 convergence bit ; 223 : (leaf 7 subleaf 1 EDX[19]) and leaf 0x24 */ ; 224 : if (has_avx10) { 00a0d 83 bd 34 05 00 00 00 cmp DWORD PTR has_avx10$32[rbp], 0 00a14 0f 84 ef 00 00 00 je $LN23@sn_get_sim ; 225 : int a10_eax = 0, a10_ebx = 0, a10_ecx = 0, a10_edx = 0; 00a1a c7 85 54 05 00 00 00 00 00 00 mov DWORD PTR a10_eax$33[rbp], 0 00a24 c7 85 74 05 00 00 00 00 00 00 mov DWORD PTR a10_ebx$34[rbp], 0 00a2e c7 85 94 05 00 00 00 00 00 00 mov DWORD PTR a10_ecx$35[rbp], 0 00a38 c7 85 b4 05 00 00 00 00 00 00 mov DWORD PTR a10_edx$36[rbp], 0 ; 226 : get_cpuid(0x24, 0, &a10_eax, &a10_ebx, &a10_ecx, &a10_edx); 00a42 48 8d 85 b4 05 00 00 lea rax, QWORD PTR a10_edx$36[rbp] 00a49 48 89 44 24 28 mov QWORD PTR [rsp+40], rax 00a4e 48 8d 85 94 05 00 00 lea rax, QWORD PTR a10_ecx$35[rbp] 00a55 48 89 44 24 20 mov QWORD PTR [rsp+32], rax 00a5a 4c 8d 8d 74 05 00 00 lea r9, QWORD PTR a10_ebx$34[rbp] 00a61 4c 8d 85 54 05 00 00 lea r8, QWORD PTR a10_eax$33[rbp] 00a68 33 d2 xor edx, edx 00a6a b9 24 00 00 00 mov ecx, 36 ; 00000024H 00a6f e8 00 00 00 00 call get_cpuid 00a74 90 npad 1 ; 227 : const int avx10_ver = a10_ebx & 0xFF; 00a75 8b 85 74 05 00 00 mov eax, DWORD PTR a10_ebx$34[rbp] 00a7b 25 ff 00 00 00 and eax, 255 ; 000000ffH 00a80 89 85 d4 05 00 00 mov DWORD PTR avx10_ver$37[rbp], eax ; 228 : if (avx10_ver >= 1) { 00a86 83 bd d4 05 00 00 01 cmp DWORD PTR avx10_ver$37[rbp], 1 00a8d 7c 7a jl SHORT $LN24@sn_get_sim ; 229 : avx10_bits |= SIMDID_AVX10 | SIMDID_AVX10_V1; 00a8f 48 8b 85 18 03 00 00 mov rax, QWORD PTR avx10_bits$[rbp] 00a96 48 83 c8 03 or rax, 3 00a9a 48 89 85 18 03 00 00 mov QWORD PTR avx10_bits$[rbp], rax ; 230 : if (avx10_ver >= 2) 00aa1 83 bd d4 05 00 00 02 cmp DWORD PTR avx10_ver$37[rbp], 2 00aa8 7c 12 jl SHORT $LN25@sn_get_sim ; 231 : avx10_bits |= SIMDID_AVX10_V2; 00aaa 48 8b 85 18 03 00 00 mov rax, QWORD PTR avx10_bits$[rbp] 00ab1 48 83 c8 04 or rax, 4 00ab5 48 89 85 18 03 00 00 mov QWORD PTR avx10_bits$[rbp], rax $LN25@sn_get_sim: ; 232 : if (a10_ebx & (1 << 17)) 00abc 8b 85 74 05 00 00 mov eax, DWORD PTR a10_ebx$34[rbp] 00ac2 25 00 00 02 00 and eax, 131072 ; 00020000H 00ac7 85 c0 test eax, eax 00ac9 74 12 je SHORT $LN26@sn_get_sim ; 233 : avx10_bits |= SIMDID_AVX10_256W; 00acb 48 8b 85 18 03 00 00 mov rax, QWORD PTR avx10_bits$[rbp] 00ad2 48 83 c8 08 or rax, 8 00ad6 48 89 85 18 03 00 00 mov QWORD PTR avx10_bits$[rbp], rax $LN26@sn_get_sim: ; 234 : if (a10_ebx & (1 << 18)) 00add 8b 85 74 05 00 00 mov eax, DWORD PTR a10_ebx$34[rbp] 00ae3 25 00 00 04 00 and eax, 262144 ; 00040000H 00ae8 85 c0 test eax, eax 00aea 74 12 je SHORT $LN27@sn_get_sim ; 235 : avx10_bits |= SIMDID_AVX10_512W; 00aec 48 8b 85 18 03 00 00 mov rax, QWORD PTR avx10_bits$[rbp] 00af3 48 83 c8 10 or rax, 16 00af7 48 89 85 18 03 00 00 mov QWORD PTR avx10_bits$[rbp], rax $LN27@sn_get_sim: ; 236 : main_lvl = SIMDID_PACK_MAIN(SIMDID_MAIN_LVL_AVX10); 00afe 48 c7 85 98 02 00 00 00 05 00 00 mov QWORD PTR main_lvl$[rbp], 1280 ; 00000500H $LN24@sn_get_sim: $LN23@sn_get_sim: $LN9@sn_get_sim: $LN3@sn_get_sim: ; 237 : } ; 238 : } ; 239 : } ; 240 : } ; 241 : ; 242 : /* uArchHi: hybrid core topology and SIMD-dual summary */ ; 243 : uint64_t uarch_bits = 0; 00b09 48 c7 85 f8 05 00 00 00 00 00 00 mov QWORD PTR uarch_bits$[rbp], 0 ; 244 : if (has_hybrid) { 00b14 83 bd 34 03 00 00 00 cmp DWORD PTR has_hybrid$[rbp], 0 00b1b 0f 84 a9 00 00 00 je $LN28@sn_get_sim ; 245 : int h_eax = 0, h_ebx = 0, h_ecx = 0, h_edx = 0; 00b21 c7 85 14 06 00 00 00 00 00 00 mov DWORD PTR h_eax$38[rbp], 0 00b2b c7 85 34 06 00 00 00 00 00 00 mov DWORD PTR h_ebx$39[rbp], 0 00b35 c7 85 54 06 00 00 00 00 00 00 mov DWORD PTR h_ecx$40[rbp], 0 00b3f c7 85 74 06 00 00 00 00 00 00 mov DWORD PTR h_edx$41[rbp], 0 ; 246 : get_cpuid(0x1A, 0, &h_eax, &h_ebx, &h_ecx, &h_edx); 00b49 48 8d 85 74 06 00 00 lea rax, QWORD PTR h_edx$41[rbp] 00b50 48 89 44 24 28 mov QWORD PTR [rsp+40], rax 00b55 48 8d 85 54 06 00 00 lea rax, QWORD PTR h_ecx$40[rbp] 00b5c 48 89 44 24 20 mov QWORD PTR [rsp+32], rax 00b61 4c 8d 8d 34 06 00 00 lea r9, QWORD PTR h_ebx$39[rbp] 00b68 4c 8d 85 14 06 00 00 lea r8, QWORD PTR h_eax$38[rbp] 00b6f 33 d2 xor edx, edx 00b71 b9 1a 00 00 00 mov ecx, 26 00b76 e8 00 00 00 00 call get_cpuid 00b7b 90 npad 1 ; 247 : unsigned core_type = (unsigned)(h_eax >> 24) & 0xFFU; 00b7c 8b 85 14 06 00 00 mov eax, DWORD PTR h_eax$38[rbp] 00b82 c1 f8 18 sar eax, 24 00b85 25 ff 00 00 00 and eax, 255 ; 000000ffH 00b8a 89 85 94 06 00 00 mov DWORD PTR core_type$42[rbp], eax ; 248 : if (core_type == 0x40) /* Intel Core / P-core → 10 */ 00b90 83 bd 94 06 00 00 40 cmp DWORD PTR core_type$42[rbp], 64 ; 00000040H 00b97 75 14 jne SHORT $LN30@sn_get_sim ; 249 : uarch_bits |= SIMDID_UARCH_HYBRID_P; 00b99 48 8b 85 f8 05 00 00 mov rax, QWORD PTR uarch_bits$[rbp] 00ba0 48 83 c8 02 or rax, 2 00ba4 48 89 85 f8 05 00 00 mov QWORD PTR uarch_bits$[rbp], rax 00bab eb 1b jmp SHORT $LN31@sn_get_sim $LN30@sn_get_sim: ; 250 : else if (core_type == 0x20) /* Intel Atom / E-core → 01 */ 00bad 83 bd 94 06 00 00 20 cmp DWORD PTR core_type$42[rbp], 32 ; 00000020H 00bb4 75 12 jne SHORT $LN32@sn_get_sim ; 251 : uarch_bits |= SIMDID_UARCH_HYBRID_E; 00bb6 48 8b 85 f8 05 00 00 mov rax, QWORD PTR uarch_bits$[rbp] 00bbd 48 83 c8 01 or rax, 1 00bc1 48 89 85 f8 05 00 00 mov QWORD PTR uarch_bits$[rbp], rax $LN32@sn_get_sim: $LN31@sn_get_sim: ; 252 : /* else unknown hybrid core type → topology stays 00 */ ; 253 : } else { 00bc8 eb 12 jmp SHORT $LN29@sn_get_sim $LN28@sn_get_sim: ; 254 : /* Confirmed non-hybrid (unified) → set both bits = 11 (numerically strongest) */ ; 255 : uarch_bits |= SIMDID_UARCH_HYBRID_P | SIMDID_UARCH_HYBRID_E; 00bca 48 8b 85 f8 05 00 00 mov rax, QWORD PTR uarch_bits$[rbp] 00bd1 48 83 c8 03 or rax, 3 00bd5 48 89 85 f8 05 00 00 mov QWORD PTR uarch_bits$[rbp], rax $LN29@sn_get_sim: ; 256 : } ; 257 : if ((avx_bits & SIMDID_AVX_DUAL) || 00bdc 48 8b 85 f8 02 00 00 mov rax, QWORD PTR avx_bits$[rbp] 00be3 48 83 e0 10 and rax, 16 00be7 48 85 c0 test rax, rax 00bea 75 13 jne SHORT $LN34@sn_get_sim 00bec 48 8b 85 b8 02 00 00 mov rax, QWORD PTR avx512_bits$[rbp] 00bf3 48 25 c0 00 00 00 and rax, 192 ; 000000c0H 00bf9 48 83 f8 40 cmp rax, 64 ; 00000040H 00bfd 75 12 jne SHORT $LN33@sn_get_sim $LN34@sn_get_sim: ; 258 : ((avx512_bits & SIMDID_AVX512_IMPL_MASK) == SIMDID_AVX512_IMPL_DUAL)) ; 259 : uarch_bits |= SIMDID_UARCH_SIMD_DUAL; 00bff 48 8b 85 f8 05 00 00 mov rax, QWORD PTR uarch_bits$[rbp] 00c06 48 83 c8 04 or rax, 4 00c0a 48 89 85 f8 05 00 00 mov QWORD PTR uarch_bits$[rbp], rax $LN33@sn_get_sim: ; 260 : ; 261 : _simdid.mask = root | manu | main_lvl | SIMDID_PACK_AVX512(avx512_bits) | 00c11 48 8b 85 78 02 00 00 mov rax, QWORD PTR manu$[rbp] 00c18 48 8b 8d 58 02 00 00 mov rcx, QWORD PTR root$[rbp] 00c1f 48 0b c8 or rcx, rax 00c22 48 8b c1 mov rax, rcx 00c25 48 0b 85 98 02 00 00 or rax, QWORD PTR main_lvl$[rbp] 00c2c 48 8b 8d b8 02 00 00 mov rcx, QWORD PTR avx512_bits$[rbp] 00c33 48 81 e1 ff ff 00 00 and rcx, 65535 ; 0000ffffH 00c3a 48 c1 e1 10 shl rcx, 16 00c3e 48 0b c1 or rax, rcx 00c41 48 8b 8d d8 02 00 00 mov rcx, QWORD PTR amx_bits$[rbp] 00c48 48 81 e1 ff 00 00 00 and rcx, 255 ; 000000ffH 00c4f 48 c1 e1 20 shl rcx, 32 ; 00000020H 00c53 48 0b c1 or rax, rcx 00c56 48 8b 8d f8 02 00 00 mov rcx, QWORD PTR avx_bits$[rbp] 00c5d 48 81 e1 ff 00 00 00 and rcx, 255 ; 000000ffH 00c64 48 c1 e1 28 shl rcx, 40 ; 00000028H 00c68 48 0b c1 or rax, rcx 00c6b 48 8b 8d 18 03 00 00 mov rcx, QWORD PTR avx10_bits$[rbp] 00c72 48 81 e1 ff 00 00 00 and rcx, 255 ; 000000ffH 00c79 48 c1 e1 30 shl rcx, 48 ; 00000030H 00c7d 48 0b c1 or rax, rcx 00c80 48 8b 8d f8 05 00 00 mov rcx, QWORD PTR uarch_bits$[rbp] 00c87 48 81 e1 ff 00 00 00 and rcx, 255 ; 000000ffH 00c8e 48 c1 e1 38 shl rcx, 56 ; 00000038H 00c92 48 0b c1 or rax, rcx 00c95 48 89 45 08 mov QWORD PTR _simdid$[rbp], rax ; 262 : SIMDID_PACK_AMX(amx_bits) | SIMDID_PACK_AVX(avx_bits) | ; 263 : SIMDID_PACK_AVX10(avx10_bits) | SIMDID_PACK_UARCH(uarch_bits); ; 264 : return _simdid; 00c99 48 8b 45 08 mov rax, QWORD PTR _simdid$[rbp] $LN35@sn_get_sim: ; 265 : } 00c9d 48 8b f8 mov rdi, rax 00ca0 48 8d 4d d0 lea rcx, QWORD PTR [rbp-48] 00ca4 48 8d 15 00 00 00 00 lea rdx, OFFSET FLAT:sn_get_simd_level_local$rtcFrameData 00cab e8 00 00 00 00 call _RTC_CheckStackVars 00cb0 48 8b c7 mov rax, rdi 00cb3 48 8b 8d d8 09 00 00 mov rcx, QWORD PTR __$ArrayPad$[rbp] 00cba 48 33 cd xor rcx, rbp 00cbd e8 00 00 00 00 call __security_check_cookie 00cc2 48 8d a5 e8 09 00 00 lea rsp, QWORD PTR [rbp+2536] 00cc9 5f pop rdi 00cca 5d pop rbp 00ccb c3 ret 0 sn_get_simd_level_local ENDP _TEXT ENDS ; Function compile flags: /Odtp /RTCsu /ZI ; File D:\platform-dev\StgSharp.Native\sn-src\simdid.x86.c ; COMDAT sn_get_simd_level_global _TEXT SEGMENT sn_get_simd_level_global PROC ; COMDAT ; 268 : { $LN4: 00000 40 55 push rbp 00002 57 push rdi 00003 48 81 ec e8 00 00 00 sub rsp, 232 ; 000000e8H 0000a 48 8d 6c 24 20 lea rbp, QWORD PTR [rsp+32] 0000f 48 8d 0d 00 00 00 00 lea rcx, OFFSET FLAT:__3EBA305F_simdid@x86@c 00016 e8 00 00 00 00 call __CheckForDebuggerJustMyCode 0001b 90 npad 1 ; 269 : if (global_simdid.mask) { 0001c 48 83 3d 00 00 00 00 00 cmp QWORD PTR global_simdid, 0 00024 74 09 je SHORT $LN2@sn_get_sim ; 270 : return global_simdid; 00026 48 8b 05 00 00 00 00 mov rax, QWORD PTR global_simdid 0002d eb 13 jmp SHORT $LN1@sn_get_sim $LN2@sn_get_sim: ; 271 : } ; 272 : global_simdid = sn_get_simd_level_local(); 0002f e8 00 00 00 00 call sn_get_simd_level_local 00034 48 89 05 00 00 00 00 mov QWORD PTR global_simdid, rax ; 273 : return global_simdid; 0003b 48 8b 05 00 00 00 00 mov rax, QWORD PTR global_simdid $LN1@sn_get_sim: ; 274 : } 00042 48 8d a5 c8 00 00 00 lea rsp, QWORD PTR [rbp+200] 00049 5f pop rdi 0004a 5d pop rbp 0004b c3 ret 0 sn_get_simd_level_global ENDP _TEXT ENDS END