From f3cfa37b1cd54ec616345b036f20fbc177efde69 Mon Sep 17 00:00:00 2001
From: Youmu Liu <105042599+Nitload-NSI@users.noreply.github.com>
Date: Fri, 15 May 2026 18:53:58 +0800
Subject: [PATCH] working on L4's tlsf

---
 .../HighPerformance/Memory/L4.CacheLine.cs    |  2 +-
 StgSharp.Common/HighPerformance/Memory/L4.cs  | 27 ++++++++++++-------
 2 files changed, 18 insertions(+), 11 deletions(-)

diff --git a/StgSharp.Common/HighPerformance/Memory/L4.CacheLine.cs b/StgSharp.Common/HighPerformance/Memory/L4.CacheLine.cs
index 3a4ad883..c42466d9 100644
--- a/StgSharp.Common/HighPerformance/Memory/L4.CacheLine.cs
+++ b/StgSharp.Common/HighPerformance/Memory/L4.CacheLine.cs
@@ -64,7 +64,7 @@ namespace StgSharp.HighPerformance.Memory
         private unsafe struct CacheLineMetadata
         {
 
-            #region lsf area
+            #region tlsf area
 
             internal const ulong Mask48Bits = 0x0000FFFFFFFFFFFF;
 
diff --git a/StgSharp.Common/HighPerformance/Memory/L4.cs b/StgSharp.Common/HighPerformance/Memory/L4.cs
index e3d80e28..4e2d14b7 100644
--- a/StgSharp.Common/HighPerformance/Memory/L4.cs
+++ b/StgSharp.Common/HighPerformance/Memory/L4.cs
@@ -41,10 +41,21 @@ namespace StgSharp.HighPerformance.Memory
         private const int PredictionCount = 2048;
         private const int PredictionLeastAhead = 1024;
 
-        // private static readonly IIntrinsicKernel _intrinsic = IIntrinsicKernel.Instance;
+        /// <summary>
+        ///   Array of metadata for each cache line, also used as metadata for tlsf allocator.
+        /// </summary>
         private readonly CacheLineMetadata* _head;
+        /// <summary>
+        ///   Count of cache lines mapped for each prediction, used for eviction policy.
+        /// </summary>
         private readonly MapArray* _mapCount;
+        /// <summary>
+        ///   Count of times each cache line is predicted, used for eviction policy.
+        /// </summary>
         private readonly PredictionArray* _predictCount;
+        /// <summary>
+        ///   Original memory view for prediction span.
+        /// </summary>
         private readonly CacheLineDescription* _prediction;
         private bool _disposed;
         private bool _exhausted;
@@ -99,7 +110,7 @@ namespace StgSharp.HighPerformance.Memory
             ptr += predictionCountSize;
 
             M512* mPtr = (M512*)_head;
-            for (uint i = 0; i < CacheLineCount; i++) {
+            for (uint i = 1; i < CacheLineCount; i++) {
                 mPtr->BroadCastFrom<ulong>(0);
             }
         }
@@ -135,17 +146,13 @@ namespace StgSharp.HighPerformance.Memory
             }
             _disposed = true;
             _map.Dispose();
+#pragma warning disable CA1816
             GC.SuppressFinalize(_bufferAllocator);
+#pragma warning restore CA1816
 
 
             // init order is fallow by align requirement of each component.
-            nuint entrySize = TLSF.RequestedAllocation;   // SIMDID, no less than 16 byte bit
-            nuint headSize = ((nuint)Unsafe.SizeOf<CacheLineMetadata>()) * CacheLineCount;   // 16 byte align
-            nuint predictionSize = ((nuint)Unsafe.SizeOf<CacheLineDescription>()) * PredictionCount;   //16 byte align
-            nuint mapSize = SwissTable.RequestedNativeMemorySize;     // 16 byte align
-            nuint predictionCountSize = (nuint)Unsafe.SizeOf<PredictionArray>();           // 16 byte align
-            nuint normalizedBufferSize = ByteCapacity;    // align to 4096 byte, page size
-            Numa.Free((void*)_baseAddress, _bindedNuma, entrySize + headSize + mapSize + predictionSize + (predictionCountSize * 2) + normalizedBufferSize);
+            Numa.Free((void*)_baseAddress, _bindedNuma, AllocSize);
             GC.SuppressFinalize(this);
         }
 
@@ -184,7 +191,7 @@ namespace StgSharp.HighPerformance.Memory
                         _ = Interlocked.Increment(ref _activeCount);
                         _ = Interlocked.Decrement(ref _aheadCount);
                         _ = Interlocked.Decrement(ref (*_mapCount)[entry->Id]);
-                        return new L4CacheLine((nuint)entry->Address, ref _activeCount, ref entry->RefCount);
+                        return new L4CacheLine((nuint)entry->Position, ref _activeCount, ref entry->RefCount);
                     } else
                     {
                         _ = Interlocked.Decrement(ref entry->RefCount);