youmuliu/stgsharp
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

Switch matrix parallel to task stealing, type and wrap are refacored, thread execution core has not yet

Browse Source
This commit is contained in:
Youmu Liu
2026-02-24 15:12:23 +08:00
parent d99c1e3aa6
commit d62e59cb93
21 changed files with 1000 additions and 965 deletions
Download Patch File Download Diff File Expand all files Collapse all files
StgSharp.Native/sn-head/StgSharpNative.h
+6 -1
View File
@@ -65,7 +65,12 @@ SN_API GLFWglproc SN_DECL loadGlfuncDefault(char *procName);
SN_API void SN_DECL unloadImageData(Image *out);
SN_API char *SN_DECL readLog(void);
SN_API void SN_DECL load_glfw_functions(GLFWFunctionTable *table);
SN_API SIMDID SN_DECL load_intrinsic_function(void *intrinsic_context);
SN_API SIMDID SN_DECL load_intrinsic_function(void *intrinsic_context, uint64_t id);
SN_API SIMDID SN_DECL sn_get_simd_level();
/* Per-core variant: always re-executes CPUID, never caches.
* Must be called on the target core (after affinity is set). */
SN_API SIMDID SN_DECL sn_get_simd_level_local();
SN_API void SN_DECL sn_set_thread_affinity(int core_id);
#ifdef __cplusplus
}
StgSharp.Native/sn-head/sn_intrincontext.x86.h
+33 -22
View File
@@ -12,6 +12,7 @@
// bits [31..16]: AVX512 Feature
// bits [39..32]: AMX Feature
// bits [47..40]: AVX Feature
// bits [55..48]: AVX10 Feature
// bits [63..56]: uArchHi / Policy (optional)
// -----------------------------------------------------------------------------
#define SIMDID_SHIFT_ROOT 0
@@ -20,6 +21,7 @@
#define SIMDID_SHIFT_AVX512 16
#define SIMDID_SHIFT_AMX 32
#define SIMDID_SHIFT_AVX 40
#define SIMDID_SHIFT_AVX10 48
#define SIMDID_SHIFT_UARCH 56
#define SIMDID_MASK_ROOT 0xFULL
@@ -28,6 +30,7 @@
#define SIMDID_MASK_AVX512 (0xFFFFULL << SIMDID_SHIFT_AVX512)
#define SIMDID_MASK_AMX (0xFFULL << SIMDID_SHIFT_AMX)
#define SIMDID_MASK_AVX (0xFFULL << SIMDID_SHIFT_AVX)
#define SIMDID_MASK_AVX10 (0xFFULL << SIMDID_SHIFT_AVX10)
#define SIMDID_MASK_UARCH (0xFFULL << SIMDID_SHIFT_UARCH)
// Root ISA (low nibble)
@@ -35,9 +38,8 @@
#define SIMDID_ROOT_X86_64 0x1
#define SIMDID_ROOT_AARCH64 0x2
#define SIMDID_ROOT_PPC64LE 0x3
#define SIMDID_ROOT_APPLESILICON 0x4
#define SIMDID_ROOT_RISCV64 0x5
#define SIMDID_ROOT_LOONGARCH 0x6
#define SIMDID_ROOT_RISCV64 0x4
#define SIMDID_ROOT_LOONGARCH 0x5
// Manufacture (x86-64 mapping; other ISAs may reinterpret)
#define SIMDID_MANU_UNKNOWN 0x0
@@ -54,31 +56,39 @@
#define SIMDID_MAIN_LVL_AVX10 0x05u
#ifndef SIMDID_AVX512_BASE
#define SIMDID_AVX512_FP16 (1U << 29)
#define SIMDID_AVX512_BF16 (1U << 28)
#define SIMDID_AVX512_VNNI (1U << 27)
#define SIMDID_AVX512_VBMI2 (1U << 26)
#define SIMDID_AVX512_VBMI (1U << 25)
#define SIMDID_AVX512_AI_RESERVED (1U << 24)
#define SIMDID_AVX512_BASE (1U << 20)
#define SIMDID_AVX512_IMPL_SHIFT 22
#define SIMDID_AVX512_IMPL_MASK (0x3U << SIMDID_AVX512_IMPL_SHIFT)
#define SIMDID_AVX512_IMPL_UNKNOWN (0x0U << SIMDID_AVX512_IMPL_SHIFT)
#define SIMDID_AVX512_IMPL_DUAL (0x1U << SIMDID_AVX512_IMPL_SHIFT)
#define SIMDID_AVX512_IMPL_NATIVE (0x2U << SIMDID_AVX512_IMPL_SHIFT)
#define SIMDID_AVX512_FP16 (1U << 13) /* relative bit 13 within [31..16] */
#define SIMDID_AVX512_BF16 (1U << 12)
#define SIMDID_AVX512_VNNI (1U << 11)
#define SIMDID_AVX512_VBMI2 (1U << 10)
#define SIMDID_AVX512_VBMI (1U << 9)
#define SIMDID_AVX512_AI_RESERVED (1U << 8)
#define SIMDID_AVX512_BASE (1U << 4)
#define SIMDID_AVX512_IMPL_SHIFT 6
#define SIMDID_AVX512_IMPL_MASK (0x3U << SIMDID_AVX512_IMPL_SHIFT)
#define SIMDID_AVX512_IMPL_UNKNOWN (0x0U << SIMDID_AVX512_IMPL_SHIFT)
#define SIMDID_AVX512_IMPL_DUAL (0x1U << SIMDID_AVX512_IMPL_SHIFT)
#define SIMDID_AVX512_IMPL_NATIVE (0x2U << SIMDID_AVX512_IMPL_SHIFT)
#endif
#ifndef SIMDID_AVX_BASE
#define SIMDID_AVX (1ULL << 40)
#define SIMDID_AVX2 (1ULL << 41)
#define SIMDID_AVX_FMA (1ULL << 42)
#define SIMDID_AVX_F16C (1ULL << 43)
#define SIMDID_AVX (1U << 0) /* relative bit 0 within [47..40] */
#define SIMDID_AVX2 (1U << 1)
#define SIMDID_AVX_FMA (1U << 2)
#define SIMDID_AVX_F16C (1U << 3)
#endif
#ifndef SIMDID_AMX_TILE
#define SIMDID_AMX_TILE (1ULL << 32)
#define SIMDID_AMX_INT8 (1ULL << 33)
#define SIMDID_AMX_BF16 (1ULL << 34)
#define SIMDID_AMX_TILE (1U << 0) /* relative bit 0 within [39..32] */
#define SIMDID_AMX_INT8 (1U << 1)
#define SIMDID_AMX_BF16 (1U << 2)
#endif
#ifndef SIMDID_AVX10_BASE
#define SIMDID_AVX10 (1U << 0) /* relative bit 0 within [55..48] */
#define SIMDID_AVX10_V1 (1U << 1)
#define SIMDID_AVX10_V2 (1U << 2)
#define SIMDID_AVX10_256W (1U << 3)
#define SIMDID_AVX10_512W (1U << 4)
#endif
// Pack helpers (define locally to avoid missing macros when included standalone)
@@ -90,6 +100,7 @@
(((uint64_t)(avx512_bits) & 0xFFFFULL) << SIMDID_SHIFT_AVX512)
#define SIMDID_PACK_AMX(amx_bits) (((uint64_t)(amx_bits) & 0xFFULL) << SIMDID_SHIFT_AMX)
#define SIMDID_PACK_AVX(avx_bits) (((uint64_t)(avx_bits) & 0xFFULL) << SIMDID_SHIFT_AVX)
#define SIMDID_PACK_AVX10(avx10_bits) (((uint64_t)(avx10_bits) & 0xFFULL) << SIMDID_SHIFT_AVX10)
#define SIMDID_PACK_UARCH(uarch_hi) (((uint64_t)(uarch_hi) & 0xFFULL) << SIMDID_SHIFT_UARCH)
#endif
StgSharp.Native/sn-head/sn_target.h
-2
View File
@@ -59,6 +59,4 @@ typedef union SIMDID {
char make_byte[8];
} SIMDID;
SN_API SIMDID SN_DECL sn_get_simd_level();
#endif // SN_TARGET