Switch matrix parallel to task stealing, type and wrap are refacored, thread execution core has not yet
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Youmu Liu
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# SIMDID (x86-64) 64-bit Specification (Completed per fixed layout)
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This document completes the **64-bit SIMDID** bit layout as specified, with emphasis on the design of the **AVX512 Feature section ([31..16])**, so it can cover the messy AVX-512 subsets while keeping branching logic compact. It also allocates an **AVX Feature byte** adjacent to the AVX512/AMX regions for AVX-family capabilities.
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This document completes the **64-bit SIMDID** bit layout as specified, with emphasis on the design of the **AVX512 Feature section ([31..16])**, so it can cover the messy AVX-512 subsets while keeping branching logic compact. It also allocates an **AVX Feature byte** adjacent to the AVX512/AMX regions for AVX-family capabilities, and an **AVX10 Feature byte** for the converged AVX10 ISA.
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> Convention: bit0 is the least significant bit (LSB). Only x86-64 interpreter semantics are defined here; the header’s Root ISA allows extension to other architectures.
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> Convention: bit0 is the least significant bit (LSB). Only x86-64 interpreter semantics are defined here; the header's Root ISA allows extension to other architectures.
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---
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@@ -10,10 +10,10 @@ This document completes the **64-bit SIMDID** bit layout as specified, with emph
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```
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SIMDID (64 bits) [63 ........................................................ 0]
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+----------+-----------+----------------+----------------+----------------+----------------+----------------+
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| [63..56] | [47..40] | [39..32] | [31..16] | [15..8] | [7..4] | [3..0] |
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| uArchHi | AVX Feat | AMX Future | AVX512 Feature | MainLevel | Manuf | Root |
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+----------+-----------+----------------+----------------+----------------+----------------+----------------+
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+----------+-----------+-----------+----------------+----------------+----------------+--------+-------+
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| [63..56] | [55..48] | [47..40] | [39..32] | [31..16] | [15..8] | [7..4] | [3..0]|
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| uArchHi | AVX10Feat | AVX Feat | AMX Future | AVX512 Feature | MainLevel | Manuf | Root |
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+----------+-----------+-----------+----------------+----------------+----------------+--------+-------+
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```
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- **[3..0] Root ISA**: Root ISA type (selects interpreter)
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@@ -22,6 +22,7 @@ SIMDID (64 bits) [63 ........................................................ 0
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- **[31..16] AVX512 Feature**: AVX-512 features/subsets/implementation form (key part)
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- **[39..32] AMX Future**: AMX features (few bits for now)
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- **[47..40] AVX Feature**: AVX-family capabilities (base requires AVX+AVX2; key extensions include FMA/F16C)
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- **[55..48] AVX10 Feature**: AVX10 converged ISA version and vector width support
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- **[63..56] uArchHi**: Optional microarchitecture/policy hints (default 0, no functional impact).
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---
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@@ -36,12 +37,11 @@ Suggested encoding (minimal usable set, expandable if needed):
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| 1 | x86-64 |
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| 2 | AArch64 |
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| 3 | PPC64LE |
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| 4 | Apple Silicon (distinct value as required) |
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| 5 | RISC-V |
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| 6 | LoongArch |
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| 7..15 | Reserved |
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| 4 | RISC-V |
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| 5 | LoongArch |
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| 6..15 | Reserved |
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> Note: Architecturally Apple Silicon is AArch64; a distinct value is provided here because the Root ISA layer may distinguish it. Interpreter choice is up to implementation.
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> Note: Apple Silicon is architecturally AArch64 and uses `Root ISA = 2`. Apple vs Qualcomm vs other AArch64 vendors are distinguished via the **Manufacture** nibble under the AArch64 interpreter, not via a separate Root ISA value.
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---
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@@ -57,7 +57,18 @@ For **x86-64**:
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| 3 | VIA/Zhaoxin |
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| 4..15 | Reserved |
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For other Root ISAs, this nibble is defined by their interpreters (e.g., Apple/Qualcomm/MediaTek for ARM).
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For **AArch64**:
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| Value | Manufacture |
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|---:|-------------|
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| 0 | Unknown/Other |
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| 1 | Apple |
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| 2 | Qualcomm |
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| 3 | MediaTek |
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| 4 | Ampere |
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| 5..15 | Reserved |
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For other Root ISAs, this nibble is defined by their interpreters.
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---
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@@ -74,10 +85,10 @@ For other Root ISAs, this nibble is defined by their interpreters (e.g., Apple/Q
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| 4 | AVX2_FMA_F16C (from this level onward, 16-bit types are supported) |
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| 5 | AVX512 (check [31..16]) |
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| 6 | AMX |
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| 7 | AVX10 |
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| 7 | AVX10 (check [55..48]) |
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| 8..255 | Reserved |
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> Scheduling suggestion: `MainLevel` is the primary switch; only when `MainLevel >= AVX512` should `AVX512 Feature` be parsed; only when `MainLevel >= AMX` should `AMX Future` be parsed. AVX Feature sits beside AMX/AVX512 and is meaningful when AVX or higher is present.
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> Scheduling suggestion: `MainLevel` is the primary switch; only when `MainLevel >= AVX512` should `AVX512 Feature` be parsed; only when `MainLevel >= AMX` should `AMX Future` be parsed; only when `MainLevel >= AVX10` should `AVX10 Feature` be parsed. AVX Feature sits beside AMX/AVX512 and is meaningful when AVX or higher is present.
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---
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@@ -109,7 +120,7 @@ Notes:
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| 2 | AVX512-NATIVE (full 512-bit ALU; 512-bit path is usable) |
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| 3 | Reserved |
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- **VBMI/VBMI2/VNNI/BF16/FP16 ([29..26])**: Commonly needed niche or AI-related small-type extensions; set as needed.
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- **VBMI/VBMI2/VNNI/BF16/FP16 ([29..25])**: Commonly needed niche or AI-related small-type extensions; set as needed.
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- **R/AI (bit 24)**: Reserved for future AI or other non-crypto extensions.
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- **[31..30], [21], [19..16]**: Reserved for future allocation.
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@@ -134,7 +145,39 @@ Rules:
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---
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## 8) "AVX512BASE" Determination (Single Check)
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## 8) AVX10 Feature Byte ([55..48], 8 bits)
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Purpose: encode the converged AVX10 ISA version and supported vector widths. AVX10 unifies and replaces the fragmented AVX-512 subset model; a single version number implies a defined set of instructions (e.g., AVX10.1 implies F+CD+VL+DQ+BW+VBMI+VBMI2+VNNI+BF16+FP16 converged). The width bits indicate what maximum vector width the hardware actually implements.
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**CPUID detection**: `CPUID leaf 0x24, subleaf 0`.
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- EBX[7:0] = AVX10 converged ISA version number (≥ 1 if supported).
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- EBX[16] = 128-bit vector support (always 1 when AVX10 is present).
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- EBX[17] = 256-bit vector support.
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- EBX[18] = 512-bit vector support.
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AVX10 Feature (bits 55..48)
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| bit | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 |
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|-----|----|----|----| ---- | ---- |----|----|------|
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| use | R | R | R | 512W | 256W | V2 | V1 | AVX10 |
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Rules:
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- **AVX10 (bit 48)**: CPU declares AVX10 converged ISA support (leaf 0x24 reports a valid version ≥ 1).
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- **V1 (bit 49)**: AVX10 version ≥ 1 (AVX10.1). Set when `EBX[7:0] >= 1`.
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- **V2 (bit 50)**: AVX10 version ≥ 2 (AVX10.2). Set when `EBX[7:0] >= 2`.
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- **256W (bit 51)**: Hardware supports 256-bit vector width for AVX10 instructions (`EBX[17]` == 1).
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- **512W (bit 52)**: Hardware supports 512-bit vector width for AVX10 instructions (`EBX[18]` == 1).
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- **[53..55]**: Reserved for future AVX10 versions (V3, V4...) or additional width/feature bits.
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> Note: When `AVX10 == 1`, the 128-bit width is always implied and does not need a dedicated bit. `V1` and `V2` are cumulative — if `V2` is set, `V1` must also be set.
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**Relationship with AVX512 Feature**:
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- AVX10 is a superset specification. When `MainLevel == AVX10`, the `AVX512 Feature` field may still be populated for backward-compatible code paths (e.g., checking `AVX512_IMPL` to select DUAL vs NATIVE 512-bit policy).
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- AVX10/256 hardware does **not** support 512-bit operations; code should check `512W` before using zmm registers.
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---
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## 9) "AVX512BASE" Determination (Single Check)
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- **Rule**: `BASE=1` implies `F+CD+VL+DQ+BW` are all present; no need for per-subset checks. Detection must keep this consistent; if not all subsets are present, set to 0.
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- **Runtime branching**:
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@@ -143,10 +186,11 @@ Rules:
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- Check `BASE`; if 0, fall back to AVX2/FMA (or treat as detection failure).
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- Check `AVX512_IMPL`: `DUAL` uses 256-bit/downclock-safe path, `NATIVE` uses 512-bit path.
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- When small-type/AI capabilities are required, consult `VNNI/BF16/FP16/VBMI/VBMI2` bits.
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- If `MainLevel == AVX10`: prefer AVX10 Feature for capability checks; `AVX512 Feature` remains valid for legacy branching.
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---
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## 9) AMX Future ([39..32], 8 bits)
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## 10) AMX Future ([39..32], 8 bits)
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A single byte is reserved; define three common bits for now, leave the rest reserved:
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@@ -161,7 +205,7 @@ When `MainLevel < AMX`, this byte can be all zeros.
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---
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## 10) uArchHi ([63..56], 8 bits)
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## 11) uArchHi ([63..56], 8 bits)
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Purpose: optional high-byte strategy field to address issues like early Intel/AMD "glue" AVX512 that are not expressible purely via CPUID subsets. Defaults to 0.
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@@ -177,7 +221,7 @@ Practical strategy for a single maintainer:
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---
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## 11) Minimal Detection-Side Fill Rules (x86-64)
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## 12) Minimal Detection-Side Fill Rules (x86-64)
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1) Set `RootISA = x86-64`, `Manufacture = Intel/AMD`.
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2) Compute `MainLevel` (per ascending rule).
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- When VNNI/BF16/FP16/VBMI/VBMI2 are detected, set the corresponding bits.
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4) If `MainLevel >= AMX`: fill the AMX byte.
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5) When AVX/AVX2 are present, populate the AVX Feature byte: set AVX and AVX2; set FMA and F16C when detected; leave reserved bits for future extensions.
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6) Use uArchHi only when additional policy is needed; otherwise leave as 0.
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6) **AVX10 detection** (requires `CPUID leaf 7 subleaf 1, EDX[19] == 1` as the AVX10 convergence bit):
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- If AVX10 is indicated, query `CPUID leaf 0x24, subleaf 0`:
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- Read `EBX[7:0]` for version number; set `AVX10`, `V1`, and optionally `V2`.
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- Read `EBX[17]` for 256-bit support → set `256W`.
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- Read `EBX[18]` for 512-bit support → set `512W`.
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- Promote `MainLevel` to `AVX10` (value 7).
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- The `AVX512 Feature` field should still be filled for backward compatibility.
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7) Use uArchHi only when additional policy is needed; otherwise leave as 0.
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---
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## 12) Choice for High Bits Reservation
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## 13) Choice for High Bits Reservation
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Currently `[31..24]` is reserved for AVX512 extensions/AI. `[47..44]` is reserved for AVX-family extensions beside the AVX byte. uArchHi `[63..56]` remains available for minimal policy hints. If IFMA or other extensions are more important, repurpose the reserved bits while keeping `BASE` and `Impl` unchanged.
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`[31..24]` is reserved for AVX512 extensions/AI. `[47..44]` is reserved for AVX-family extensions beside the AVX byte. `[55..53]` is reserved for future AVX10 versions. uArchHi `[63..56]` remains available for minimal policy hints. If IFMA or other extensions are more important, repurpose the reserved bits while keeping `BASE`, `Impl`, and `AVX10` core bits unchanged.
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