Switch matrix parallel to task stealing, type and wrap are refacored, thread execution core has not yet
This commit is contained in:
Youmu Liu
@@ -1,8 +1,8 @@
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# SIMDID (x86-64) 64-bit Specification (Completed per fixed layout)
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This document completes the **64-bit SIMDID** bit layout as specified, with emphasis on the design of the **AVX512 Feature section ([31..16])**, so it can cover the messy AVX-512 subsets while keeping branching logic compact. It also allocates an **AVX Feature byte** adjacent to the AVX512/AMX regions for AVX-family capabilities.
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This document completes the **64-bit SIMDID** bit layout as specified, with emphasis on the design of the **AVX512 Feature section ([31..16])**, so it can cover the messy AVX-512 subsets while keeping branching logic compact. It also allocates an **AVX Feature byte** adjacent to the AVX512/AMX regions for AVX-family capabilities, and an **AVX10 Feature byte** for the converged AVX10 ISA.
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> Convention: bit0 is the least significant bit (LSB). Only x86-64 interpreter semantics are defined here; the header’s Root ISA allows extension to other architectures.
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> Convention: bit0 is the least significant bit (LSB). Only x86-64 interpreter semantics are defined here; the header's Root ISA allows extension to other architectures.
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---
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@@ -10,10 +10,10 @@ This document completes the **64-bit SIMDID** bit layout as specified, with emph
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```
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SIMDID (64 bits) [63 ........................................................ 0]
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+----------+-----------+----------------+----------------+----------------+----------------+----------------+
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| [63..56] | [47..40] | [39..32] | [31..16] | [15..8] | [7..4] | [3..0] |
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| uArchHi | AVX Feat | AMX Future | AVX512 Feature | MainLevel | Manuf | Root |
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+----------+-----------+----------------+----------------+----------------+----------------+----------------+
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+----------+-----------+-----------+----------------+----------------+----------------+--------+-------+
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| [63..56] | [55..48] | [47..40] | [39..32] | [31..16] | [15..8] | [7..4] | [3..0]|
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| uArchHi | AVX10Feat | AVX Feat | AMX Future | AVX512 Feature | MainLevel | Manuf | Root |
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+----------+-----------+-----------+----------------+----------------+----------------+--------+-------+
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```
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- **[3..0] Root ISA**: Root ISA type (selects interpreter)
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@@ -22,6 +22,7 @@ SIMDID (64 bits) [63 ........................................................ 0
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- **[31..16] AVX512 Feature**: AVX-512 features/subsets/implementation form (key part)
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- **[39..32] AMX Future**: AMX features (few bits for now)
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- **[47..40] AVX Feature**: AVX-family capabilities (base requires AVX+AVX2; key extensions include FMA/F16C)
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- **[55..48] AVX10 Feature**: AVX10 converged ISA version and vector width support
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- **[63..56] uArchHi**: Optional microarchitecture/policy hints (default 0, no functional impact).
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---
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@@ -36,12 +37,11 @@ Suggested encoding (minimal usable set, expandable if needed):
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| 1 | x86-64 |
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| 2 | AArch64 |
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| 3 | PPC64LE |
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| 4 | Apple Silicon (distinct value as required) |
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| 5 | RISC-V |
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| 6 | LoongArch |
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| 7..15 | Reserved |
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| 4 | RISC-V |
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| 5 | LoongArch |
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| 6..15 | Reserved |
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> Note: Architecturally Apple Silicon is AArch64; a distinct value is provided here because the Root ISA layer may distinguish it. Interpreter choice is up to implementation.
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> Note: Apple Silicon is architecturally AArch64 and uses `Root ISA = 2`. Apple vs Qualcomm vs other AArch64 vendors are distinguished via the **Manufacture** nibble under the AArch64 interpreter, not via a separate Root ISA value.
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---
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@@ -57,7 +57,18 @@ For **x86-64**:
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| 3 | VIA/Zhaoxin |
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| 4..15 | Reserved |
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For other Root ISAs, this nibble is defined by their interpreters (e.g., Apple/Qualcomm/MediaTek for ARM).
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For **AArch64**:
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| Value | Manufacture |
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|---:|-------------|
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| 0 | Unknown/Other |
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| 1 | Apple |
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| 2 | Qualcomm |
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| 3 | MediaTek |
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| 4 | Ampere |
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| 5..15 | Reserved |
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For other Root ISAs, this nibble is defined by their interpreters.
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---
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@@ -74,10 +85,10 @@ For other Root ISAs, this nibble is defined by their interpreters (e.g., Apple/Q
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| 4 | AVX2_FMA_F16C (from this level onward, 16-bit types are supported) |
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| 5 | AVX512 (check [31..16]) |
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| 6 | AMX |
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| 7 | AVX10 |
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| 7 | AVX10 (check [55..48]) |
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| 8..255 | Reserved |
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> Scheduling suggestion: `MainLevel` is the primary switch; only when `MainLevel >= AVX512` should `AVX512 Feature` be parsed; only when `MainLevel >= AMX` should `AMX Future` be parsed. AVX Feature sits beside AMX/AVX512 and is meaningful when AVX or higher is present.
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> Scheduling suggestion: `MainLevel` is the primary switch; only when `MainLevel >= AVX512` should `AVX512 Feature` be parsed; only when `MainLevel >= AMX` should `AMX Future` be parsed; only when `MainLevel >= AVX10` should `AVX10 Feature` be parsed. AVX Feature sits beside AMX/AVX512 and is meaningful when AVX or higher is present.
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---
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@@ -109,7 +120,7 @@ Notes:
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| 2 | AVX512-NATIVE (full 512-bit ALU; 512-bit path is usable) |
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| 3 | Reserved |
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- **VBMI/VBMI2/VNNI/BF16/FP16 ([29..26])**: Commonly needed niche or AI-related small-type extensions; set as needed.
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- **VBMI/VBMI2/VNNI/BF16/FP16 ([29..25])**: Commonly needed niche or AI-related small-type extensions; set as needed.
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- **R/AI (bit 24)**: Reserved for future AI or other non-crypto extensions.
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- **[31..30], [21], [19..16]**: Reserved for future allocation.
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@@ -134,7 +145,39 @@ Rules:
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---
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## 8) "AVX512BASE" Determination (Single Check)
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## 8) AVX10 Feature Byte ([55..48], 8 bits)
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Purpose: encode the converged AVX10 ISA version and supported vector widths. AVX10 unifies and replaces the fragmented AVX-512 subset model; a single version number implies a defined set of instructions (e.g., AVX10.1 implies F+CD+VL+DQ+BW+VBMI+VBMI2+VNNI+BF16+FP16 converged). The width bits indicate what maximum vector width the hardware actually implements.
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**CPUID detection**: `CPUID leaf 0x24, subleaf 0`.
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- EBX[7:0] = AVX10 converged ISA version number (≥ 1 if supported).
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- EBX[16] = 128-bit vector support (always 1 when AVX10 is present).
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- EBX[17] = 256-bit vector support.
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- EBX[18] = 512-bit vector support.
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AVX10 Feature (bits 55..48)
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| bit | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 |
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|-----|----|----|----| ---- | ---- |----|----|------|
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| use | R | R | R | 512W | 256W | V2 | V1 | AVX10 |
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Rules:
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- **AVX10 (bit 48)**: CPU declares AVX10 converged ISA support (leaf 0x24 reports a valid version ≥ 1).
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- **V1 (bit 49)**: AVX10 version ≥ 1 (AVX10.1). Set when `EBX[7:0] >= 1`.
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- **V2 (bit 50)**: AVX10 version ≥ 2 (AVX10.2). Set when `EBX[7:0] >= 2`.
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- **256W (bit 51)**: Hardware supports 256-bit vector width for AVX10 instructions (`EBX[17]` == 1).
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- **512W (bit 52)**: Hardware supports 512-bit vector width for AVX10 instructions (`EBX[18]` == 1).
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- **[53..55]**: Reserved for future AVX10 versions (V3, V4...) or additional width/feature bits.
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> Note: When `AVX10 == 1`, the 128-bit width is always implied and does not need a dedicated bit. `V1` and `V2` are cumulative — if `V2` is set, `V1` must also be set.
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**Relationship with AVX512 Feature**:
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- AVX10 is a superset specification. When `MainLevel == AVX10`, the `AVX512 Feature` field may still be populated for backward-compatible code paths (e.g., checking `AVX512_IMPL` to select DUAL vs NATIVE 512-bit policy).
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- AVX10/256 hardware does **not** support 512-bit operations; code should check `512W` before using zmm registers.
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---
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## 9) "AVX512BASE" Determination (Single Check)
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- **Rule**: `BASE=1` implies `F+CD+VL+DQ+BW` are all present; no need for per-subset checks. Detection must keep this consistent; if not all subsets are present, set to 0.
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- **Runtime branching**:
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@@ -143,10 +186,11 @@ Rules:
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- Check `BASE`; if 0, fall back to AVX2/FMA (or treat as detection failure).
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- Check `AVX512_IMPL`: `DUAL` uses 256-bit/downclock-safe path, `NATIVE` uses 512-bit path.
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- When small-type/AI capabilities are required, consult `VNNI/BF16/FP16/VBMI/VBMI2` bits.
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- If `MainLevel == AVX10`: prefer AVX10 Feature for capability checks; `AVX512 Feature` remains valid for legacy branching.
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---
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## 9) AMX Future ([39..32], 8 bits)
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## 10) AMX Future ([39..32], 8 bits)
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A single byte is reserved; define three common bits for now, leave the rest reserved:
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@@ -161,7 +205,7 @@ When `MainLevel < AMX`, this byte can be all zeros.
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---
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## 10) uArchHi ([63..56], 8 bits)
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## 11) uArchHi ([63..56], 8 bits)
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Purpose: optional high-byte strategy field to address issues like early Intel/AMD "glue" AVX512 that are not expressible purely via CPUID subsets. Defaults to 0.
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@@ -177,7 +221,7 @@ Practical strategy for a single maintainer:
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---
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## 11) Minimal Detection-Side Fill Rules (x86-64)
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## 12) Minimal Detection-Side Fill Rules (x86-64)
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1) Set `RootISA = x86-64`, `Manufacture = Intel/AMD`.
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2) Compute `MainLevel` (per ascending rule).
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@@ -189,10 +233,17 @@ Practical strategy for a single maintainer:
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- When VNNI/BF16/FP16/VBMI/VBMI2 are detected, set the corresponding bits.
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4) If `MainLevel >= AMX`: fill the AMX byte.
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5) When AVX/AVX2 are present, populate the AVX Feature byte: set AVX and AVX2; set FMA and F16C when detected; leave reserved bits for future extensions.
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6) Use uArchHi only when additional policy is needed; otherwise leave as 0.
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6) **AVX10 detection** (requires `CPUID leaf 7 subleaf 1, EDX[19] == 1` as the AVX10 convergence bit):
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- If AVX10 is indicated, query `CPUID leaf 0x24, subleaf 0`:
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- Read `EBX[7:0]` for version number; set `AVX10`, `V1`, and optionally `V2`.
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- Read `EBX[17]` for 256-bit support → set `256W`.
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- Read `EBX[18]` for 512-bit support → set `512W`.
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- Promote `MainLevel` to `AVX10` (value 7).
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- The `AVX512 Feature` field should still be filled for backward compatibility.
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7) Use uArchHi only when additional policy is needed; otherwise leave as 0.
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---
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## 12) Choice for High Bits Reservation
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## 13) Choice for High Bits Reservation
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Currently `[31..24]` is reserved for AVX512 extensions/AI. `[47..44]` is reserved for AVX-family extensions beside the AVX byte. uArchHi `[63..56]` remains available for minimal policy hints. If IFMA or other extensions are more important, repurpose the reserved bits while keeping `BASE` and `Impl` unchanged.
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`[31..24]` is reserved for AVX512 extensions/AI. `[47..44]` is reserved for AVX-family extensions beside the AVX byte. `[55..53]` is reserved for future AVX10 versions. uArchHi `[63..56]` remains available for minimal policy hints. If IFMA or other extensions are more important, repurpose the reserved bits while keeping `BASE`, `Impl`, and `AVX10` core bits unchanged.
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@@ -28,21 +28,21 @@
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<UseDebugLibraries>true</UseDebugLibraries>
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<CharacterSet>Unicode</CharacterSet>
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<WholeProgramOptimization>false</WholeProgramOptimization>
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<PlatformToolset>v145</PlatformToolset>
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<PlatformToolset>v143</PlatformToolset>
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</PropertyGroup>
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<PropertyGroup Condition="'$(Configuration)|$(Platform)'=='Release|x64'" Label="Configuration">
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<ConfigurationType>DynamicLibrary</ConfigurationType>
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<UseDebugLibraries>false</UseDebugLibraries>
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<WholeProgramOptimization>true</WholeProgramOptimization>
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<CharacterSet>Unicode</CharacterSet>
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<PlatformToolset>v145</PlatformToolset>
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<PlatformToolset>v143</PlatformToolset>
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</PropertyGroup>
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<PropertyGroup Condition="'$(Configuration)|$(Platform)'=='PerformanceDebug|x64'" Label="Configuration">
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<ConfigurationType>DynamicLibrary</ConfigurationType>
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<UseDebugLibraries>false</UseDebugLibraries>
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<WholeProgramOptimization>true</WholeProgramOptimization>
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<CharacterSet>Unicode</CharacterSet>
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<PlatformToolset>v145</PlatformToolset>
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||||
<PlatformToolset>v143</PlatformToolset>
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</PropertyGroup>
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||||
<Import Project="$(VCTargetsPath)\Microsoft.Cpp.props" />
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<ImportGroup Label="ExtensionSettings">
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@@ -171,6 +171,7 @@
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<ClCompile Include="sn-src\cpuid.x86.c" />
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<ClCompile Include="sn-src\sn_native.c" />
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<ClCompile Include="sn-src\str_string.c" />
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<ClCompile Include="sn-src\t.affinity.c" />
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<ClCompile Include="sn-src\vector.c" />
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<ClCompile Include="sn-src\vector_dot.c" />
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</ItemGroup>
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@@ -194,6 +195,7 @@
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<Library Include="lib\glfw\glfw3_mt.lib" />
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</ItemGroup>
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<ItemGroup>
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<None Include="naming.md" />
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<None Include="SIMDID.x86.md" />
|
||||
</ItemGroup>
|
||||
<Import Project="$(VCTargetsPath)\Microsoft.Cpp.targets" />
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@@ -66,6 +66,9 @@
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<ClCompile Include="sn-src\m.fma_tile.x86.c">
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<Filter>源文件</Filter>
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</ClCompile>
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<ClCompile Include="sn-src\t.affinity.c">
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<Filter>源文件</Filter>
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</ClCompile>
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</ItemGroup>
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<ItemGroup>
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<ClInclude Include="sn-head\gl.h">
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@@ -120,5 +123,8 @@
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<None Include="SIMDID.x86.md">
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<Filter>Document</Filter>
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</None>
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<None Include="naming.md">
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<Filter>Document</Filter>
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||||
</None>
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||||
</ItemGroup>
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||||
</Project>
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@@ -65,7 +65,12 @@ SN_API GLFWglproc SN_DECL loadGlfuncDefault(char *procName);
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SN_API void SN_DECL unloadImageData(Image *out);
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SN_API char *SN_DECL readLog(void);
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SN_API void SN_DECL load_glfw_functions(GLFWFunctionTable *table);
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SN_API SIMDID SN_DECL load_intrinsic_function(void *intrinsic_context);
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SN_API SIMDID SN_DECL load_intrinsic_function(void *intrinsic_context, uint64_t id);
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SN_API SIMDID SN_DECL sn_get_simd_level();
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/* Per-core variant: always re-executes CPUID, never caches.
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* Must be called on the target core (after affinity is set). */
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SN_API SIMDID SN_DECL sn_get_simd_level_local();
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SN_API void SN_DECL sn_set_thread_affinity(int core_id);
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#ifdef __cplusplus
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}
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@@ -12,6 +12,7 @@
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// bits [31..16]: AVX512 Feature
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// bits [39..32]: AMX Feature
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// bits [47..40]: AVX Feature
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// bits [55..48]: AVX10 Feature
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// bits [63..56]: uArchHi / Policy (optional)
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// -----------------------------------------------------------------------------
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#define SIMDID_SHIFT_ROOT 0
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@@ -20,6 +21,7 @@
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#define SIMDID_SHIFT_AVX512 16
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#define SIMDID_SHIFT_AMX 32
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#define SIMDID_SHIFT_AVX 40
|
||||
#define SIMDID_SHIFT_AVX10 48
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#define SIMDID_SHIFT_UARCH 56
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#define SIMDID_MASK_ROOT 0xFULL
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@@ -28,6 +30,7 @@
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#define SIMDID_MASK_AVX512 (0xFFFFULL << SIMDID_SHIFT_AVX512)
|
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#define SIMDID_MASK_AMX (0xFFULL << SIMDID_SHIFT_AMX)
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#define SIMDID_MASK_AVX (0xFFULL << SIMDID_SHIFT_AVX)
|
||||
#define SIMDID_MASK_AVX10 (0xFFULL << SIMDID_SHIFT_AVX10)
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#define SIMDID_MASK_UARCH (0xFFULL << SIMDID_SHIFT_UARCH)
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||||
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||||
// Root ISA (low nibble)
|
||||
@@ -35,9 +38,8 @@
|
||||
#define SIMDID_ROOT_X86_64 0x1
|
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#define SIMDID_ROOT_AARCH64 0x2
|
||||
#define SIMDID_ROOT_PPC64LE 0x3
|
||||
#define SIMDID_ROOT_APPLESILICON 0x4
|
||||
#define SIMDID_ROOT_RISCV64 0x5
|
||||
#define SIMDID_ROOT_LOONGARCH 0x6
|
||||
#define SIMDID_ROOT_RISCV64 0x4
|
||||
#define SIMDID_ROOT_LOONGARCH 0x5
|
||||
|
||||
// Manufacture (x86-64 mapping; other ISAs may reinterpret)
|
||||
#define SIMDID_MANU_UNKNOWN 0x0
|
||||
@@ -54,31 +56,39 @@
|
||||
#define SIMDID_MAIN_LVL_AVX10 0x05u
|
||||
|
||||
#ifndef SIMDID_AVX512_BASE
|
||||
#define SIMDID_AVX512_FP16 (1U << 29)
|
||||
#define SIMDID_AVX512_BF16 (1U << 28)
|
||||
#define SIMDID_AVX512_VNNI (1U << 27)
|
||||
#define SIMDID_AVX512_VBMI2 (1U << 26)
|
||||
#define SIMDID_AVX512_VBMI (1U << 25)
|
||||
#define SIMDID_AVX512_AI_RESERVED (1U << 24)
|
||||
#define SIMDID_AVX512_BASE (1U << 20)
|
||||
#define SIMDID_AVX512_IMPL_SHIFT 22
|
||||
#define SIMDID_AVX512_IMPL_MASK (0x3U << SIMDID_AVX512_IMPL_SHIFT)
|
||||
#define SIMDID_AVX512_IMPL_UNKNOWN (0x0U << SIMDID_AVX512_IMPL_SHIFT)
|
||||
#define SIMDID_AVX512_IMPL_DUAL (0x1U << SIMDID_AVX512_IMPL_SHIFT)
|
||||
#define SIMDID_AVX512_IMPL_NATIVE (0x2U << SIMDID_AVX512_IMPL_SHIFT)
|
||||
#define SIMDID_AVX512_FP16 (1U << 13) /* relative bit 13 within [31..16] */
|
||||
#define SIMDID_AVX512_BF16 (1U << 12)
|
||||
#define SIMDID_AVX512_VNNI (1U << 11)
|
||||
#define SIMDID_AVX512_VBMI2 (1U << 10)
|
||||
#define SIMDID_AVX512_VBMI (1U << 9)
|
||||
#define SIMDID_AVX512_AI_RESERVED (1U << 8)
|
||||
#define SIMDID_AVX512_BASE (1U << 4)
|
||||
#define SIMDID_AVX512_IMPL_SHIFT 6
|
||||
#define SIMDID_AVX512_IMPL_MASK (0x3U << SIMDID_AVX512_IMPL_SHIFT)
|
||||
#define SIMDID_AVX512_IMPL_UNKNOWN (0x0U << SIMDID_AVX512_IMPL_SHIFT)
|
||||
#define SIMDID_AVX512_IMPL_DUAL (0x1U << SIMDID_AVX512_IMPL_SHIFT)
|
||||
#define SIMDID_AVX512_IMPL_NATIVE (0x2U << SIMDID_AVX512_IMPL_SHIFT)
|
||||
#endif
|
||||
|
||||
#ifndef SIMDID_AVX_BASE
|
||||
#define SIMDID_AVX (1ULL << 40)
|
||||
#define SIMDID_AVX2 (1ULL << 41)
|
||||
#define SIMDID_AVX_FMA (1ULL << 42)
|
||||
#define SIMDID_AVX_F16C (1ULL << 43)
|
||||
#define SIMDID_AVX (1U << 0) /* relative bit 0 within [47..40] */
|
||||
#define SIMDID_AVX2 (1U << 1)
|
||||
#define SIMDID_AVX_FMA (1U << 2)
|
||||
#define SIMDID_AVX_F16C (1U << 3)
|
||||
#endif
|
||||
|
||||
#ifndef SIMDID_AMX_TILE
|
||||
#define SIMDID_AMX_TILE (1ULL << 32)
|
||||
#define SIMDID_AMX_INT8 (1ULL << 33)
|
||||
#define SIMDID_AMX_BF16 (1ULL << 34)
|
||||
#define SIMDID_AMX_TILE (1U << 0) /* relative bit 0 within [39..32] */
|
||||
#define SIMDID_AMX_INT8 (1U << 1)
|
||||
#define SIMDID_AMX_BF16 (1U << 2)
|
||||
#endif
|
||||
|
||||
#ifndef SIMDID_AVX10_BASE
|
||||
#define SIMDID_AVX10 (1U << 0) /* relative bit 0 within [55..48] */
|
||||
#define SIMDID_AVX10_V1 (1U << 1)
|
||||
#define SIMDID_AVX10_V2 (1U << 2)
|
||||
#define SIMDID_AVX10_256W (1U << 3)
|
||||
#define SIMDID_AVX10_512W (1U << 4)
|
||||
#endif
|
||||
|
||||
// Pack helpers (define locally to avoid missing macros when included standalone)
|
||||
@@ -90,6 +100,7 @@
|
||||
(((uint64_t)(avx512_bits) & 0xFFFFULL) << SIMDID_SHIFT_AVX512)
|
||||
#define SIMDID_PACK_AMX(amx_bits) (((uint64_t)(amx_bits) & 0xFFULL) << SIMDID_SHIFT_AMX)
|
||||
#define SIMDID_PACK_AVX(avx_bits) (((uint64_t)(avx_bits) & 0xFFULL) << SIMDID_SHIFT_AVX)
|
||||
#define SIMDID_PACK_AVX10(avx10_bits) (((uint64_t)(avx10_bits) & 0xFFULL) << SIMDID_SHIFT_AVX10)
|
||||
#define SIMDID_PACK_UARCH(uarch_hi) (((uint64_t)(uarch_hi) & 0xFFULL) << SIMDID_SHIFT_UARCH)
|
||||
#endif
|
||||
|
||||
|
||||
@@ -59,6 +59,4 @@ typedef union SIMDID {
|
||||
char make_byte[8];
|
||||
} SIMDID;
|
||||
|
||||
SN_API SIMDID SN_DECL sn_get_simd_level();
|
||||
|
||||
#endif // SN_TARGET
|
||||
|
||||
@@ -1,5 +1,6 @@
|
||||
#include "sn_target.h"
|
||||
#include "sn_intrinsic.h"
|
||||
#include "StgSharpNative.h"
|
||||
|
||||
static SIMDID global_simdid = { 0 };
|
||||
|
||||
@@ -76,11 +77,9 @@ static int is_intel_native_avx512(int family, int model)
|
||||
}
|
||||
}
|
||||
|
||||
SN_API SIMDID SN_DECL sn_get_simd_level()
|
||||
SN_API SIMDID SN_DECL sn_get_simd_level_local()
|
||||
{
|
||||
if (global_simdid.mask) {
|
||||
return global_simdid;
|
||||
}
|
||||
SIMDID _simdid = { 0 };
|
||||
|
||||
int eax = 0, ebx = 0, ecx = 0, edx = 0;
|
||||
|
||||
@@ -114,6 +113,7 @@ SN_API SIMDID SN_DECL sn_get_simd_level()
|
||||
uint64_t avx512_bits = 0;
|
||||
uint64_t amx_bits = 0;
|
||||
uint64_t avx_bits = 0;
|
||||
uint64_t avx10_bits = 0;
|
||||
|
||||
/* Baseline main level */
|
||||
if (has_sse42)
|
||||
@@ -135,15 +135,17 @@ SN_API SIMDID SN_DECL sn_get_simd_level()
|
||||
const int has_vbmi = (ecx & (1 << 1)) != 0;
|
||||
const int has_vbmi2 = (ecx & (1 << 6)) != 0;
|
||||
|
||||
/* leaf 7, subleaf 1 for BF16/FP16 */
|
||||
/* AMX in leaf 7 subleaf 0 EDX bits 24/25/26 — capture before
|
||||
overwriting regs with subleaf 1 */
|
||||
const int has_amx_tile = (edx & (1 << 24)) != 0;
|
||||
const int has_amx_int8 = (edx & (1 << 25)) != 0;
|
||||
const int has_amx_bf16 = (edx & (1 << 22)) != 0;
|
||||
|
||||
/* leaf 7, subleaf 1 for BF16/FP16/AVX10 convergence */
|
||||
get_cpuid(7, 1, &eax, &ebx, &ecx, &edx);
|
||||
const int has_bf16 = (eax & (1 << 5)) != 0; /* AVX512_BF16 */
|
||||
const int has_fp16 = (eax & (1 << 23)) != 0; /* AVX512_FP16 */
|
||||
|
||||
/* AMX in leaf 7 subleaf 0 EDX bits 24/25/26 */
|
||||
const int has_amx_tile = (edx & (1 << 24)) != 0;
|
||||
const int has_amx_int8 = (edx & (1 << 25)) != 0;
|
||||
const int has_amx_bf16 = (edx & (1 << 26)) != 0;
|
||||
const int has_avx10 = (edx & (1 << 19)) != 0; /* AVX10 convergence */
|
||||
|
||||
if (has_avx2) {
|
||||
avx_bits |= SIMDID_AVX2;
|
||||
@@ -194,11 +196,39 @@ SN_API SIMDID SN_DECL sn_get_simd_level()
|
||||
amx_bits |= SIMDID_AMX_BF16;
|
||||
main_lvl = SIMDID_PACK_MAIN(SIMDID_MAIN_LVL_AMX);
|
||||
}
|
||||
|
||||
/* AVX10 detection — requires AVX10 convergence bit
|
||||
(leaf 7 subleaf 1 EDX[19]) and leaf 0x24 */
|
||||
if (has_avx10) {
|
||||
int a10_eax = 0, a10_ebx = 0, a10_ecx = 0, a10_edx = 0;
|
||||
get_cpuid(0x24, 0, &a10_eax, &a10_ebx, &a10_ecx, &a10_edx);
|
||||
const int avx10_ver = a10_ebx & 0xFF;
|
||||
if (avx10_ver >= 1) {
|
||||
avx10_bits |= SIMDID_AVX10 | SIMDID_AVX10_V1;
|
||||
if (avx10_ver >= 2)
|
||||
avx10_bits |= SIMDID_AVX10_V2;
|
||||
if (a10_ebx & (1 << 17))
|
||||
avx10_bits |= SIMDID_AVX10_256W;
|
||||
if (a10_ebx & (1 << 18))
|
||||
avx10_bits |= SIMDID_AVX10_512W;
|
||||
main_lvl = SIMDID_PACK_MAIN(SIMDID_MAIN_LVL_AVX10);
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
global_simdid.mask = root | manu | main_lvl | SIMDID_PACK_AVX512(avx512_bits) |
|
||||
SIMDID_PACK_AMX(amx_bits) | SIMDID_PACK_AVX(avx_bits);
|
||||
_simdid.mask = root | manu | main_lvl | SIMDID_PACK_AVX512(avx512_bits) |
|
||||
SIMDID_PACK_AMX(amx_bits) | SIMDID_PACK_AVX(avx_bits) |
|
||||
SIMDID_PACK_AVX10(avx10_bits);
|
||||
return _simdid;
|
||||
}
|
||||
|
||||
SN_API SIMDID SN_DECL sn_get_simd_level()
|
||||
{
|
||||
if (global_simdid.mask) {
|
||||
return global_simdid;
|
||||
}
|
||||
global_simdid = sn_get_simd_level_local();
|
||||
return global_simdid;
|
||||
}
|
||||
|
||||
|
||||
@@ -14,14 +14,21 @@
|
||||
#endif // _MSC_VER
|
||||
|
||||
PRIVATE void load_intrinsic_sse(sn_intrinsic *context, SIMDID id);
|
||||
PRIVATE void load_intrinsic_avx_dual(sn_intrinsic *context, SIMDID id);
|
||||
PRIVATE void load_intrinsic_avx(sn_intrinsic *context, SIMDID id);
|
||||
PRIVATE void load_intrinsic_512_dual(sn_intrinsic *context, SIMDID id);
|
||||
PRIVATE void load_intrinsic_512(sn_intrinsic *context, SIMDID id);
|
||||
|
||||
SN_API SIMDID load_intrinsic_function(void *intrinsic_context)
|
||||
SN_API SIMDID load_intrinsic_function(void *intrinsic_context, uint64_t id)
|
||||
{
|
||||
sn_null_assert(intrinsic_context);
|
||||
|
||||
SIMDID simdid = sn_get_simd_level();
|
||||
SIMDID simdid;
|
||||
if (id) {
|
||||
simdid.mask = id;
|
||||
} else {
|
||||
simdid = sn_get_simd_level();
|
||||
}
|
||||
|
||||
sn_intrinsic *context = (sn_intrinsic *)intrinsic_context;
|
||||
|
||||
@@ -33,6 +40,8 @@ SN_API SIMDID load_intrinsic_function(void *intrinsic_context)
|
||||
load_intrinsic_avx(context, simdid);
|
||||
break;
|
||||
case SIMDID_MAIN_LVL_AVX512:
|
||||
case SIMDID_MAIN_LVL_AMX:
|
||||
case SIMDID_MAIN_LVL_AVX10:
|
||||
load_intrinsic_512(context, simdid);
|
||||
break;
|
||||
}
|
||||
@@ -75,8 +84,8 @@ void load_intrinsic_sse(sn_intrinsic *context, SIMDID id)
|
||||
void load_intrinsic_avx(sn_intrinsic *context, SIMDID id)
|
||||
{
|
||||
char avx_seg = id.make_byte[5];
|
||||
char is_fma = (avx_seg & 1 << 3) != 0;
|
||||
char is_f16c = (avx_seg & 1 << 4) != 0;
|
||||
char is_fma = (avx_seg & SIMDID_AVX_FMA) != 0;
|
||||
char is_f16c = (avx_seg & SIMDID_AVX_F16C) != 0;
|
||||
|
||||
context->city_hash_simplify = city_hash_simplify_sse;
|
||||
context->factorial_simd = factorial_simd_sse;
|
||||
|
||||
@@ -7,34 +7,8 @@
|
||||
|
||||
#define _FMA_SELECT(i) _MM_SHUFFLE(i, i, i, i)
|
||||
|
||||
/*
|
||||
[MethodImpl(MethodImplOptions.AggressiveInlining)]
|
||||
internal static unsafe MatrixKernel<T>* GetKernelAddressUnsafe<T>(
|
||||
MatrixKernel<T>* buffer,
|
||||
int colLength,
|
||||
int x,
|
||||
int y
|
||||
) where T : unmanaged, INumber<T>
|
||||
{
|
||||
return buffer + (colLength * x + y);
|
||||
}
|
||||
*/
|
||||
|
||||
#define GET_INDEX(col_len, x, y) (col_len * x + y)
|
||||
|
||||
/*
|
||||
for (int k = 0; k < commonK; k += 1) {
|
||||
NativeIntrinsic.Context
|
||||
.mat[f64].kernel_fma(
|
||||
(MatrixPanel*)GetKernelAddressUnsafe((MatrixKernel<double>*)leftBuffer,
|
||||
ansHeight, k, j),
|
||||
(MatrixPanel*)GetKernelAddressUnsafe((MatrixKernel<double>*)rightBuffer,
|
||||
commonK, j, k),
|
||||
(MatrixPanel*)GetKernelAddressUnsafe((MatrixKernel<double>*)ansBuffer,
|
||||
ansHeight, i, j));
|
||||
}
|
||||
*/
|
||||
|
||||
// float
|
||||
|
||||
DECLARE_KERTILE_PROC_LEFT_RIGHT_ANS(float, sse, , fma)
|
||||
|
||||
@@ -0,0 +1,31 @@
|
||||
#include "sn_target.h"
|
||||
#include "StgSharpNative.h"
|
||||
|
||||
#if SN_IS_OS(SN_OS_LINUX)
|
||||
#define _GNU_SOURCE
|
||||
#include <pthread.h>
|
||||
#include <sched.h>
|
||||
#endif
|
||||
|
||||
/* Pin the calling thread to a single logical processor.
|
||||
* core_id: zero-based logical processor index.
|
||||
* Silently ignored if core_id is out of range or the OS call fails. */
|
||||
SN_API void SN_DECL sn_set_thread_affinity(int core_id)
|
||||
{
|
||||
if (core_id < 0)
|
||||
return;
|
||||
|
||||
#if SN_IS_OS(SN_OS_WINDOWS)
|
||||
/* windows.h already included via sn_internal.h */
|
||||
if (core_id >= 64)
|
||||
return;
|
||||
DWORD_PTR mask = (DWORD_PTR)1 << core_id;
|
||||
SetThreadAffinityMask(GetCurrentThread(), mask);
|
||||
|
||||
#elif SN_IS_OS(SN_OS_LINUX)
|
||||
cpu_set_t set;
|
||||
CPU_ZERO(&set);
|
||||
CPU_SET(core_id, &set);
|
||||
pthread_setaffinity_np(pthread_self(), sizeof(set), &set);
|
||||
#endif
|
||||
}
|
||||
Reference in New Issue
Block a user