add simd id
This commit is contained in:
Youmu Liu
@@ -1,4 +1,4 @@
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#ifndef SSC_INTRIN
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#ifndef SSC_INTRIN
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#define SSC_INTRIN
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#define SSC_INTRIN_HEAD
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@@ -22,7 +22,8 @@
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(LASTTWO(source - 1) << 6) | (LASTTWO(target - 1) << 4) | (LAST(reset3) << 3) | \
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(LAST(reset2) << 2) | (LAST(reset1) << 1) | LAST(reset0)
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#define SSE_INSERT_SIMPLE(source, target) SSE_INSERT(source, target, 0, 0, 0, 0)
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#define M256_PERMUTE(s3, s2, s1, s0) (LASTTWO(s3) << 6) | (LASTTWO(s2) << 4) | (LASTTWO(s1) << 2) | (LASTTWO(s0)
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#define M256_PERMUTE(s3, s2, s1, s0) \
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((LASTTWO(s3) << 6) | (LASTTWO(s2) << 4) | (LASTTWO(s1) << 2) | (LASTTWO(s0)))
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#define BIT_CVRT(pack, index, T) *(T *)(pack->data + index)
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#define zero_vec _mm_setzero_ps()
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#define zero_vec_256 _mm256_setzero_ps()
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@@ -92,8 +93,8 @@ typedef struct matrix_task matrix_task;
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#if defined(__cplusplus)
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static_assert(sizeof(matrix_task) == 128, "matrix_parallel_task_package size mismatch");
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#elif defined(__STDC_VERSION__) && __STDC_VERSION__ >= 201112L
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_Static_assert(sizeof(MAT_TASK(float)) == 128, "matrix_parallel_task_package size mismatch");
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#elif defined(__STDC_VERSION__)
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static_assert(sizeof(MAT_TASK(float)) == 128, "matrix_parallel_task_package size mismatch");
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#endif
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#pragma region matrix buffer operation function type
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@@ -197,6 +198,114 @@ typedef void(SN_DECL *VECTORNORMALIZEPROC)(__m128 *source, __m128 *target);
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typedef void(SN_DECL *DOTPROC)(void *transpose, __m128 *vector, __m128 *ans);
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typedef uint64_t(SN_DECL *FACTORIALROC)(int n);
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#pragma region string
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typedef int(SN_DECL *HASH)(byte const *str, int length);
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typedef int(SN_DECL *INDEX_PAIR)(short const *stram, uint32_t target, int length);
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#pragma endregion
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typedef struct mat_intrinsic {
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BUF_PROC_LRA buffer_add;
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BUF_PROC_AS buffer_fill;
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BUF_PROC_RAS buffer_scalar_mul;
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BUF_PROC_LRA buffer_sub;
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KER_PROC_RA buffer_transpose;
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PANEL_PROC build_panel;
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PANEL_PROC clear_panel;
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PNL_PROC_LRA panel_fma;
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PIVOTPROC pivot;
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PANEL_PROC store_panel;
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} mat_intrinsic;
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// Mirrors C# IntrinsicContext field order so managed/unmanaged layouts stay in sync.
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typedef struct sn_intrinsic {
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HASH city_hash_simplify;
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FACTORIALROC factorial_simd;
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INDEX_PAIR index_pair;
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VECTORNORMALIZEPROC vec_f32_normalize_3;
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mat_intrinsic mat[4];
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} sn_intrinsic;
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typedef enum elment_type { F32 = 0, F64 = 1, I32 = 2, I64 = 3 } element_type;
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typedef enum most_advanced_instruction {
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#ifdef _MSC_VER
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SSE = __IA_SUPPORT_SSE42,
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AVX256 = __IA_SUPPORT_VECTOR256,
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AVX512 = __IA_SUPPORT_VECTOR512,
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NEON
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#else
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SSE,
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AVX256,
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AVX512,
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NEON
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#endif
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} most_advanced_instruction;
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#include "sn_target.h"
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#if SN_IS_ARCH(SN_ARCH_X86_64)
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// -----------------------------------------------------------------------------
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// SIMDID layout helpers (see SIMDID.simd.md)
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// bits [3..0] : Root ISA
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// bits [7..4] : Manufacture (ISA-specific)
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// bits [15..8] : MainLevel (monotonic capability)
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// bits [31..16]: AVX512 Feature
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// bits [39..32]: AMX Feature
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// bits [63..40]: uArch / Policy (optional)
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// -----------------------------------------------------------------------------
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#define SIMDID_SHIFT_ROOT 0
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#define SIMDID_SHIFT_MANU 4
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#define SIMDID_SHIFT_MAIN 8
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#define SIMDID_SHIFT_AVX512 16
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#define SIMDID_SHIFT_AMX 32
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#define SIMDID_SHIFT_UARCH 40
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#define SIMDID_MASK_ROOT 0xFULL
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#define SIMDID_MASK_MANU (0xFULL << SIMDID_SHIFT_MANU)
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#define SIMDID_MASK_MAIN (0xFFULL << SIMDID_SHIFT_MAIN)
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#define SIMDID_MASK_AVX512 (0xFFFFULL << SIMDID_SHIFT_AVX512)
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#define SIMDID_MASK_AMX (0xFFULL << SIMDID_SHIFT_AMX)
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#define SIMDID_MASK_UARCH (0xFFFFFFULL << SIMDID_SHIFT_UARCH)
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// Root ISA (low nibble)
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#define SIMDID_ROOT_UNKNOWN 0x0
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#define SIMDID_ROOT_X86_64 0x1
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#define SIMDID_ROOT_AARCH64 0x2
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#define SIMDID_ROOT_PPC64LE 0x3
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#define SIMDID_ROOT_APPLESILICON 0x4
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#define SIMDID_ROOT_RISCV64 0x5
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#define SIMDID_ROOT_LOONGARCH 0x6
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// Manufacture (x86-64 mapping; other ISAs may reinterpret)
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#define SIMDID_MANU_UNKNOWN 0x0
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#define SIMDID_MANU_INTEL 0x1
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#define SIMDID_MANU_AMD 0x2
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#define SIMDID_MANU_VIA 0x3
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// MainLevel (ordinal, shared bits 8..15; not bit-flags)
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#define SIMDID_MAIN_LVL_NONE 0x00u
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#define SIMDID_MAIN_LVL_SSE 0x01u /* SSE1..SSE4.2 */
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#define SIMDID_MAIN_LVL_AVX2 0x02u
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#define SIMDID_MAIN_LVL_AVX2_FMA 0x03u
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#define SIMDID_MAIN_LVL_AVX2_FMA_F16C 0x04u /* 16-bit scalar/vector ready */
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#define SIMDID_MAIN_LVL_AVX512 0x05u
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#define SIMDID_MAIN_LVL_AMX 0x06u
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#define SIMDID_MAIN_LVL_AVX10 0x07u
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/* Pre-shifted helpers for convenience when constructing SIMDID */
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#define SIMDID_MAIN_ENC_NONE SIMDID_PACK_MAIN(SIMDID_MAIN_LVL_NONE)
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#define SIMDID_MAIN_ENC_SSE SIMDID_PACK_MAIN(SIMDID_MAIN_LVL_SSE)
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#define SIMDID_MAIN_ENC_AVX2 SIMDID_PACK_MAIN(SIMDID_MAIN_LVL_AVX2)
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#define SIMDID_MAIN_ENC_AVX2_FMA SIMDID_PACK_MAIN(SIMDID_MAIN_LVL_AVX2_FMA)
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#define SIMDID_MAIN_ENC_AVX2_FMA_F16C SIMDID_PACK_MAIN(SIMDID_MAIN_LVL_AVX2_FMA_F16C)
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#define SIMDID_MAIN_ENC_AVX512 SIMDID_PACK_MAIN(SIMDID_MAIN_LVL_AVX512)
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#define SIMDID_MAIN_ENC_AMX SIMDID_PACK_MAIN(SIMDID_MAIN_LVL_AMX)
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#define SIMDID_MAIN_ENC_AVX10 SIMDID_PACK_MAIN(SIMDID_MAIN_LVL_AVX10)
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#pragma region matix function
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INTERNAL void f32_normalize(VEC(float) * source, VEC(float) * target);
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@@ -281,85 +390,15 @@ INTERNAL void SN_DECL dot_42_avx(MAT_KERNEL(float) const *transpose, __m128 cons
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#pragma region string
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typedef int(SN_DECL *HASH)(byte const *str, int length);
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typedef int(SN_DECL *INDEX_PAIR)(short const *stram, uint32_t target, int length);
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INTERNAL int SN_DECL city_hash_simplify_sse(byte const *str, int length);
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INTERNAL int SN_DECL index_pair_sse(short const *str, uint32_t target, int length);
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INTERNAL int SN_DECL index_pair_sse(short const *stram, uint32_t target, int length);
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#pragma endregion
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typedef struct mat_intrinsic {
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BUF_PROC_LRA buffer_add;
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BUF_PROC_AS buffer_fill;
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BUF_PROC_RAS buffer_scalar_mul;
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BUF_PROC_LRA buffer_sub;
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KER_PROC_RA buffer_transpose;
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PANEL_PROC build_panel;
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PANEL_PROC clear_panel;
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PNL_PROC_LRA panel_fma;
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PIVOTPROC pivot;
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PANEL_PROC store_panel;
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} mat_intrinsic;
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// Mirrors C# IntrinsicContext field order so managed/unmanaged layouts stay in sync.
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typedef struct sn_intrinsic {
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HASH city_hash_simplify;
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FACTORIALROC factorial_simd;
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INDEX_PAIR index_pair;
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VECTORNORMALIZEPROC vec_f32_normalize_3;
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mat_intrinsic mat[4];
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} sn_intrinsic;
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typedef enum elment_type { F32 = 0, F64 = 1, I32 = 2, I64 = 3 } element_type;
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typedef enum most_advanced_instruction {
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#ifdef _MSC_VER
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SSE = __IA_SUPPORT_SSE42,
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AVX256 = __IA_SUPPORT_VECTOR256,
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AVX512 = __IA_SUPPORT_VECTOR512,
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NEON
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#else
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SSE,
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AVX256,
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AVX512,
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NEON
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#endif
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} most_advanced_instruction;
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#include "sn_target.h"
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typedef enum intrinsic_level { SIMD0 = 0 } intrinsic_level;
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#if SN_IS_ARCH(SN_ARCH_X86_64)
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typedef enum intrinsic_level {
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// No SIMD support, will cause error if used in matrix operations
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SIMD0 = 0,
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// SSE4.2 support
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SIMD1 = 1,
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// AVX2 support
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SIMD2 = 2,
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// AVX2 and AVX2-FMA support
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SIMD3 = 3,
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// AVX2-16C support based on SIMD3
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SIMD4 = 4,
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// AVX-512-dual support
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SIMD5 = 5,
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// AVX-512-native support
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SIMD6 = 6,
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// AVX-512 with 8/16-wide support
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SIMD7 = 7,
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// AMX support
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SIMD8 = 8,
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// AVX-10 support
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SIMD9 = 9,
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// future use
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SIMD_MAX = 10
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} intrinsic_level;
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#else
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typedef enum intrinsic_level {
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} intrinsic_level;
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#endif
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#endif
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