L4 completely add support for multi predictor, working on ver 5 mat para

StgSharp.Common/HighPerformance/Memory/L4.cs

@@ -26,6 +26,7 @@
 // -----------------------------------------------------------------------
 // -----------------------------------------------------------------------
 using StgSharp.Collections;
+using StgSharp.Common.HighPerformance.ProcessorAbstraction;
 using System.Data;
 using System.Runtime.InteropServices;
 
@@ -49,14 +50,20 @@ namespace StgSharp.HighPerformance.Memory
         private int _activeCount;
 
         private int _aheadCount;
+
+        private readonly int _bindedNuma;
         private int _maxId;
         private volatile int _prefetching;
         private readonly nuint _baseAddress;
         private readonly SwissTable _map;
         private readonly UnmanagedStack<int> _idMux;
 
-        public L4()
+        public L4(
+               int bindedNuma
+        )
         {
+            _bindedNuma = bindedNuma;
+
             // init order is fallow by align requirement of each component.
             nuint cacheSize = ((nuint)Unsafe.SizeOf<CacheLineData>()) * CacheLineCount;   // SIMDID, no less than 16 byte bit
             nuint entrySize = ((nuint)Unsafe.SizeOf<CacheLineHead>()) * CacheLineCount;   // 16 byte align
@@ -67,7 +74,7 @@ namespace StgSharp.HighPerformance.Memory
 
             // malloc all memory at once, and free at once in Dispose.
             // This is to avoid fragmentation and improve performance.
-            _baseAddress = (nuint)NativeMemory.AlignedAlloc(cacheSize + entrySize + stackSize + mapSize + predictionSize + rrpvSize, 16);
+            _baseAddress = (nuint)Numa.Alloc(bindedNuma, cacheSize + entrySize + stackSize + mapSize + predictionSize + rrpvSize);
             nuint ptr = _baseAddress;
 
             // init all components with the buffer, and move the buffer pointer forward.
@@ -86,6 +93,8 @@ namespace StgSharp.HighPerformance.Memory
             ptr += stackSize;
         }
 
+        public static nuint AllocSize { get; }
+
         // public IL4Predict PrefetchPredict { get; set; }
 
         [MethodImpl(MethodImplOptions.AggressiveInlining)]
@@ -114,7 +123,15 @@ namespace StgSharp.HighPerformance.Memory
             _disposed = true;
             _map.Dispose();
             _idMux.Dispose();
-            NativeMemory.AlignedFree((void*)_baseAddress);
+
+
+            nuint cacheSize = ((nuint)Unsafe.SizeOf<CacheLineData>()) * CacheLineCount;   // SIMDID, no less than 16 byte bit
+            nuint entrySize = ((nuint)Unsafe.SizeOf<CacheLineHead>()) * CacheLineCount;   // 16 byte align
+            nuint predictionSize = ((nuint)Unsafe.SizeOf<CacheLinePrediction>()) * PredictionCount;   //16 byte align
+            nuint mapSize = (nuint)SwissTable.RequestedNativeMemorySize;     // 16 byte align
+            nuint rrpvSize = (nuint)Unsafe.SizeOf<EvictionArray>();           // 16 byte align
+            nuint stackSize = ((nuint)sizeof(int)) * CacheLineCount;                      // int align
+            Numa.Free((void*)_baseAddress, _bindedNuma, cacheSize + entrySize + stackSize + mapSize + predictionSize + rrpvSize);
             GC.SuppressFinalize(this);
         }
 
@@ -164,10 +181,6 @@ namespace StgSharp.HighPerformance.Memory
 
         private partial void Prefetch();
 
-        private partial bool TestHit(
-                             nuint origin
-        );
-
         private struct CacheLineData
         {