fma code added
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@@ -141,22 +141,26 @@ typedef void(SN_DECL *PNL_PROC_RAS)(mat_panel *right, mat_panel *ans, scalar_pac
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#define PNL_PROC(T_type, T_arch, T_op_name) T_type##_pnl_##T_op_name##_##T_arch
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#define DECLARE_PNL_PROC_LEFT_RIGHT_ANS(T_type, T_arch, T_op_name) \
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INTERNAL void SN_DECL PNL_PROC(T_type, T_arch, T_op_name)( \
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MAT_PANEL##T_arch##(T_type) const *left, MAT_PANEL##T_arch##(T_type) const *right, \
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MAT_PANEL##T_arch##(T_type) *restrict ans)
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#define DECLARE_PNL_PROC_LEFT_RIGHT_ANS(T_type, T_arch, T_op_name) \
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INTERNAL void SN_DECL PNL_PROC(T_type, T_arch, T_op_name)( \
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MAT_PANEL##T_arch##(T_type) const *left, MAT_PANEL##T_arch##(T_type) const *right, \
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MAT_PANEL##T_arch##(T_type) *restrict ans)
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#define DECLARE_PNL_PROC_LEFT_RIGHT_ANS_SCALAR(T_type, T_arch, T_op_name) \
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INTERNAL void SN_DECL PNL_PROC(T_type, T_arch, T_op_name)( \
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MAT_PANEL##T_arch##(T_type) const *left, MAT_PANEL##T_arch##(T_type) const *right, \
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MAT_PANEL##T_arch##(T_type) *restrict ans, scalar_pack const *scalar)
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#define DECLARE_PNL_PROC_LEFT_RIGHT_ANS_SCALAR(T_type, T_arch, T_op_name) \
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INTERNAL void SN_DECL PNL_PROC(T_type, T_arch, T_op_name)( \
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MAT_PANEL##T_arch##(T_type) const *left, MAT_PANEL##T_arch##(T_type) const *right, \
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MAT_PANEL##T_arch##(T_type) *restrict ans, scalar_pack const *scalar)
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#define DECLARE_PNL_PROC_LEFT_RIGHT_ANS(T_type, T_arch, T_op_name) \
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INTERNAL void SN_DECL PNL_PROC(T_type, T_arch, \
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T_op_name)(MAT_PANEL_##T_arch##(T_type) const *left, \
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MAT_PANEL_##T_arch##(T_type) const *right, \
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MAT_PANEL_##T_arch##(T_type) *restrict ans)
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#define DECLARE_PNL_PROC_LEFT_RIGHT_ANS(T_type, T_arch, T_op_name) \
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INTERNAL void SN_DECL PNL_PROC(T_type, T_arch, \
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T_op_name)(MAT_PANEL_##T_arch##(T_type) const *left, \
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MAT_PANEL_##T_arch##(T_type) const *right, \
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MAT_PANEL_##T_arch##(T_type) *restrict ans)
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#define DECLARE_PNL_PROC_LEFT_RIGHT_ANS_SCALAR(T_type, T_arch, T_op_name) \
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INTERNAL void SN_DECL PNL_PROC(T_type, T_arch, T_op_name)( \
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MAT_PANEL_##T_arch##(T_type) const *left, \
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MAT_PANEL_##T_arch##(T_type) const *right, \
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MAT_PANEL_##T_arch##(T_type) *restrict ans, scalar_pack const *scalar)
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#define DECLARE_PNL_PROC_LEFT_RIGHT_ANS_SCALAR(T_type, T_arch, T_op_name) \
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INTERNAL void SN_DECL PNL_PROC(T_type, T_arch, T_op_name)( \
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MAT_PANEL_##T_arch##(T_type) const *left, \
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MAT_PANEL_##T_arch##(T_type) const *right, \
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MAT_PANEL_##T_arch##(T_type) *restrict ans, scalar_pack const *scalar)
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#pragma endregion
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@@ -219,7 +223,8 @@ DECLARE_BUF_PROC_ANS_SCALAR(float, 512, fill);
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#pragma region fma
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DECLARE_KER_PROC_LEFT_RIGHT_ANS(float, sse, fma);
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DECLARE_PNL_PROC_LEFT_RIGHT_ANS(float, sse, fma);
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DECLARE_PNL_PROC_LEFT_RIGHT_ANS(float, avx, fma);
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#pragma endregion
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@@ -67,15 +67,19 @@ typedef MAT_KERNEL(uint64_t) sn_zero_kernel_u64;
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/* SSE panel layout: column-major buffer holding 4 logical columns with MINQ=4.
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Columns: each column packs up to four scalars so ALIGN equals sizeof(__m128).
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Alignment: every column boundary lands on a 16-byte multiple for XMM loads. */
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#define MAT_PANEL_SSE(T) SN_ALIGNAS(16) MAT_PANEL_SQ_MIN_NOALIGN(T, __m128, 4)
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#define MAT_PANEL_sse(T) SN_ALIGNAS(16) MAT_PANEL_SQ_MIN_NOALIGN(T, __m128, 4)
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/* AVX2 panel layout: column-major buffer holding 8 logical columns with MINQ=8.
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Columns: each column stores eight elements via two 256-bit chunks when T is 32-bit.
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Alignment: column starts are 32-byte aligned so AVX2 loads/stores remain contiguous. */
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#define MAT_PANEL_AVX(T) SN_ALIGNAS(32) MAT_PANEL_SQ_MIN_NOALIGN(T, __m256, 8)
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#define MAT_PANEL_avx(T) SN_ALIGNAS(32) MAT_PANEL_SQ_MIN_NOALIGN(T, __m256, 8)
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/* AVX2 panel layout: column-major buffer holding 8 logical columns with MINQ=8.
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Columns: each column stores eight elements via two 256-bit chunks when T is 32-bit.
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Alignment: column starts are 32-byte aligned so AVX2 loads/stores remain contiguous. */
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#define MAT_PANEL_avx_fma(T) SN_ALIGNAS(32) MAT_PANEL_SQ_MIN_NOALIGN(T, __m256, 8)
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/* AVX-512 panel layout: column-major buffer holding 8 or more columns depending on T.
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Columns: each column expands to ceil(Q/lanes) ZMM chunks; default MINQ=8 keeps double-wide tiles.
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Columns: each column expands to ceil(Q/lanes) ZMM chunks; default MINQ=8 keeps doublse-wide tiles.
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Alignment: column starts sit on 64-byte boundaries to match AVX-512 streaming access. */
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#define MAT_PANEL_512(T) SN_ALIGNAS(64) MAT_PANEL_SQ_MIN_NOALIGN(T, __m512, 8)
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#define MAT_PANEL_512(T) SN_ALIGNAS(64) MAT_PANEL_SQ_MIN_NOALIGN(T, __m512, 8)
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/* Global zero kernel declaration (defined in dllmain.c), aligned to 64 bytes */
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#ifdef __cplusplus
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@@ -113,7 +117,7 @@ extern __declspec(align(64)) sn_zero_kernel_u64 SN_ZERO_KERNEL;
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int col_index, int row_index)
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/* Declarations for AVX float variant */
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DECLARE_BUILD_PANEL(AVX, float);
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DECLARE_STORE_PANEL(AVX, float);
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DECLARE_BUILD_PANEL(avx, float);
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DECLARE_STORE_PANEL(avx, float);
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#endif /* SN_MATKERNEL */
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