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solution to length unfixed cacheline in l4

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Nitload
2026-04-19 02:30:35 +08:00
parent f2560f3d5b
commit 5fc8e62f28
14 changed files with 421 additions and 532 deletions
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StgSharp.Common/HighPerformance/Memory/L4.cs
+40 -47
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@@ -1,35 +1,41 @@
//-----------------------------------------------------------------------
// -----------------------------------------------------------------------
// file="L4"
// file="L4.cs"
// Project: StgSharp
// AuthorGroup: Nitload
// Copyright (c) Nitload. All rights reserved.
// AuthorGroup: Nitload Space
// Copyright (c) Nitload Space. All rights reserved.
//
// Permission is hereby granted, free of charge, to any person obtaining a copy
// of this software and associated documentation files (the "Software"), to deal
// in the Software without restriction, including without limitation the rights
// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
//
// The above copyright notice and this permission notice shall be included in all
// copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
// SOFTWARE.
// Permission is hereby granted, free of charge, to any person
// obtaining a copy of this software and associated documentation
// files (the “Software”), to deal in the Software without restriction,
// including without limitation the rights to use, copy, modify, merge,
// publish, distribute, sublicense, and/or sell copies of the Software,
// and to permit persons to whom the Software is furnished to do so,
// subject to the following conditions:
//
// The above copyright notice and
// this permission notice shall be included in all copies
// or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED “AS IS”,
// WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
// DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
// ARISING FROM, OUT OF OR IN CONNECTION WITH
// THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
//
// -----------------------------------------------------------------------
// -----------------------------------------------------------------------
using StgSharp.Collections;
using StgSharp.Common.HighPerformance.ProcessorAbstraction;
using StgSharp.Mathematics.Memory;
using System.Data;
using System.Runtime.InteropServices;
using HLSF = StgSharp.Mathematics.Memory.HybridLayerSegregatedFitAllocator;
namespace StgSharp.HighPerformance.Memory
{
public sealed unsafe partial class L4 : IDisposable
@@ -40,13 +46,13 @@ namespace StgSharp.HighPerformance.Memory
private const int PredictionLeastAhead = 1024;
private static readonly IIntrinsicKernel _intrinsic = IIntrinsicKernel.Instance;
private readonly CacheLineData* _data;
private readonly EvictionArray* _eviction;
private readonly CacheLineHead* _head;
private readonly CacheLinePrediction* _prediction;
private bool _disposed;
private bool _exhausted;
private readonly HLSF _bufferAllocator;
private int _activeCount;
private int _aheadCount;
@@ -55,20 +61,19 @@ namespace StgSharp.HighPerformance.Memory
private int _maxId;
private volatile int _prefetching;
private readonly nuint _baseAddress;
private readonly SlabAllocator<HLSF.Entry> _entryManager;
private readonly SwissTable _map;
private readonly UnmanagedStack<int> _idMux;
public L4(
int bindedNuma
)
public L4(int bindedNuma, nuint bufferSize = 8192 * 8192, int align = 16, int maxCacheLineSize = 8192)
{
_bindedNuma = bindedNuma;
// init order is fallow by align requirement of each component.
nuint cacheSize = ((nuint)Unsafe.SizeOf<CacheLineData>()) * CacheLineCount; // SIMDID, no less than 16 byte bit
nuint cacheSize = ((nuint)Unsafe.SizeOf<HLSF.Entry>()) * CacheLineCount; // SIMDID, no less than 16 byte bit
nuint entrySize = ((nuint)Unsafe.SizeOf<CacheLineHead>()) * CacheLineCount; // 16 byte align
nuint predictionSize = ((nuint)Unsafe.SizeOf<CacheLinePrediction>()) * PredictionCount; //16 byte align
nuint mapSize = (nuint)SwissTable.RequestedNativeMemorySize; // 16 byte align
nuint mapSize = SwissTable.RequestedNativeMemorySize; // 16 byte align
nuint rrpvSize = (nuint)Unsafe.SizeOf<EvictionArray>(); // 16 byte align
nuint stackSize = ((nuint)sizeof(int)) * CacheLineCount; // int align
@@ -78,8 +83,10 @@ namespace StgSharp.HighPerformance.Memory
nuint ptr = _baseAddress;
// init all components with the buffer, and move the buffer pointer forward.
_entryManager = SlabAllocator.FromBuffer();
_bufferAllocator = new HLSF(cacheSize, align, maxCacheLineSize, (void*)_baseAddress, static _ => { });
nuint _buffer = _baseAddress;
_data = (CacheLineData*)_buffer;
ptr += cacheSize;
_head = (CacheLineHead*)ptr;
ptr += entrySize;
@@ -98,9 +105,7 @@ namespace StgSharp.HighPerformance.Memory
// public IL4Predict PrefetchPredict { get; set; }
[MethodImpl(MethodImplOptions.AggressiveInlining)]
public void ContinueOnce(
L4CacheLine line
)
public void ContinueOnce(L4CacheLine line)
{
if (line.Address > 0) {
_ = Interlocked.Decrement(ref _aheadCount);
@@ -123,12 +128,13 @@ namespace StgSharp.HighPerformance.Memory
_disposed = true;
_map.Dispose();
_idMux.Dispose();
_bufferAllocator.Dispose();
nuint cacheSize = ((nuint)Unsafe.SizeOf<CacheLineData>()) * CacheLineCount; // SIMDID, no less than 16 byte bit
nuint entrySize = ((nuint)Unsafe.SizeOf<CacheLineHead>()) * CacheLineCount; // 16 byte align
nuint predictionSize = ((nuint)Unsafe.SizeOf<CacheLinePrediction>()) * PredictionCount; //16 byte align
nuint mapSize = (nuint)SwissTable.RequestedNativeMemorySize; // 16 byte align
nuint mapSize = SwissTable.RequestedNativeMemorySize; // 16 byte align
nuint rrpvSize = (nuint)Unsafe.SizeOf<EvictionArray>(); // 16 byte align
nuint stackSize = ((nuint)sizeof(int)) * CacheLineCount; // int align
Numa.Free((void*)_baseAddress, _bindedNuma, cacheSize + entrySize + stackSize + mapSize + predictionSize + rrpvSize);
@@ -136,9 +142,7 @@ namespace StgSharp.HighPerformance.Memory
}
[MethodImpl(MethodImplOptions.AggressiveInlining)]
public L4CacheLine Map(
nuint origin
)
public L4CacheLine Map(nuint origin)
{
if ((_aheadCount < PredictionLeastAhead) && !_exhausted)
{
@@ -181,13 +185,6 @@ namespace StgSharp.HighPerformance.Memory
private partial void Prefetch();
private struct CacheLineData
{
private fixed byte Data[8192];
}
}
public ref struct L4CacheLine : IDisposable
@@ -197,11 +194,7 @@ namespace StgSharp.HighPerformance.Memory
private ref int _refCount;
private nuint _handle;
internal L4CacheLine(
nuint handle,
ref int activeCount,
ref int cacheRefCount
)
internal L4CacheLine(nuint handle, ref int activeCount, ref int cacheRefCount)
{
_handle = handle;
_refCount = ref cacheRefCount;