daily update on 20230316 by nitload youmu
This commit is contained in:
Nitload
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Microsoft Visual Studio Solution File, Format Version 12.00
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# Visual Studio Version 17
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VisualStudioVersion = 17.3.32825.248
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MinimumVisualStudioVersion = 10.0.40219.1
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Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "AsmMath", "AsmMath\AsmMath.vcxproj", "{CCB13811-6071-41C7-89A1-8B38FB5E4F88}"
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Global
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Debug|x64 = Debug|x64
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{CCB13811-6071-41C7-89A1-8B38FB5E4F88}.Debug|x86.ActiveCfg = Debug|Win32
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{CCB13811-6071-41C7-89A1-8B38FB5E4F88}.Debug|x86.Build.0 = Debug|Win32
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{CCB13811-6071-41C7-89A1-8B38FB5E4F88}.Release|x64.ActiveCfg = Release|x64
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{CCB13811-6071-41C7-89A1-8B38FB5E4F88}.Release|x64.Build.0 = Release|x64
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{CCB13811-6071-41C7-89A1-8B38FB5E4F88}.Release|x86.ActiveCfg = Release|Win32
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{CCB13811-6071-41C7-89A1-8B38FB5E4F88}.Release|x86.Build.0 = Release|Win32
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EndGlobalSection
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GlobalSection(SolutionProperties) = preSolution
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<?xml version="1.0" encoding="utf-8"?>
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<Project DefaultTargets="Build" xmlns="http://schemas.microsoft.com/developer/msbuild/2003">
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<ItemGroup Label="ProjectConfigurations">
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<ProjectConfiguration Include="Debug|Win32">
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<Configuration>Debug</Configuration>
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<Platform>Win32</Platform>
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</ProjectConfiguration>
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<ProjectConfiguration Include="Release|Win32">
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<Configuration>Release</Configuration>
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<Platform>Win32</Platform>
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</ProjectConfiguration>
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<ProjectConfiguration Include="Debug|x64">
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<Configuration>Debug</Configuration>
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<Platform>x64</Platform>
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<ProjectConfiguration Include="Release|x64">
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<Configuration>Release</Configuration>
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<Platform>x64</Platform>
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</ItemGroup>
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<PropertyGroup Label="Globals">
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<VCProjectVersion>16.0</VCProjectVersion>
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<Keyword>Win32Proj</Keyword>
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<ProjectGuid>{ccb13811-6071-41c7-89a1-8b38fb5e4f88}</ProjectGuid>
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<RootNamespace>AsmMath</RootNamespace>
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<WindowsTargetPlatformVersion>10.0</WindowsTargetPlatformVersion>
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</PropertyGroup>
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<Import Project="$(VCTargetsPath)\Microsoft.Cpp.Default.props" />
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<PropertyGroup Condition="'$(Configuration)|$(Platform)'=='Debug|Win32'" Label="Configuration">
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<ImportGroup Label="ExtensionSettings">
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<PropertyGroup Label="UserMacros" />
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<ClCompile>
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<WarningLevel>Level3</WarningLevel>
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<SDLCheck>true</SDLCheck>
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<PreprocessorDefinitions>WIN32;_DEBUG;_CONSOLE;%(PreprocessorDefinitions)</PreprocessorDefinitions>
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<ConformanceMode>true</ConformanceMode>
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</ClCompile>
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<Link>
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<SubSystem>Console</SubSystem>
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<GenerateDebugInformation>true</GenerateDebugInformation>
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</Link>
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<ItemDefinitionGroup Condition="'$(Configuration)|$(Platform)'=='Release|Win32'">
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<ClCompile>
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<WarningLevel>Level3</WarningLevel>
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<FunctionLevelLinking>true</FunctionLevelLinking>
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<IntrinsicFunctions>true</IntrinsicFunctions>
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<SDLCheck>true</SDLCheck>
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<PreprocessorDefinitions>WIN32;NDEBUG;_CONSOLE;%(PreprocessorDefinitions)</PreprocessorDefinitions>
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<ConformanceMode>true</ConformanceMode>
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</ClCompile>
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<Link>
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<SubSystem>Console</SubSystem>
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<EnableCOMDATFolding>true</EnableCOMDATFolding>
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<OptimizeReferences>true</OptimizeReferences>
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<GenerateDebugInformation>true</GenerateDebugInformation>
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<ConformanceMode>true</ConformanceMode>
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</ClCompile>
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<Link>
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<SubSystem>Console</SubSystem>
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<GenerateDebugInformation>true</GenerateDebugInformation>
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<EntryPointSymbol>main</EntryPointSymbol>
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<IntrinsicFunctions>true</IntrinsicFunctions>
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<SDLCheck>true</SDLCheck>
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<PreprocessorDefinitions>NDEBUG;_CONSOLE;%(PreprocessorDefinitions)</PreprocessorDefinitions>
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<ConformanceMode>true</ConformanceMode>
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<Link>
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<SubSystem>Console</SubSystem>
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<OptimizeReferences>true</OptimizeReferences>
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<GenerateDebugInformation>true</GenerateDebugInformation>
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</Link>
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</ItemDefinitionGroup>
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<ItemGroup>
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<None Include="Sqrt0001.asm" />
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</ItemGroup>
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<Import Project="$(VCTargetsPath)\Microsoft.Cpp.targets" />
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<ImportGroup Label="ExtensionTargets">
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<Import Project="$(VCTargetsPath)\BuildCustomizations\masm.targets" />
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@@ -0,0 +1,22 @@
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<?xml version="1.0" encoding="utf-8"?>
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<Project ToolsVersion="4.0" xmlns="http://schemas.microsoft.com/developer/msbuild/2003">
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<ItemGroup>
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<Filter Include="源文件">
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<UniqueIdentifier>{4FC737F1-C7A5-4376-A066-2A32D752A2FF}</UniqueIdentifier>
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||||
<Extensions>cpp;c;cc;cxx;c++;cppm;ixx;def;odl;idl;hpj;bat;asm;asmx</Extensions>
|
||||
</Filter>
|
||||
<Filter Include="头文件">
|
||||
<UniqueIdentifier>{93995380-89BD-4b04-88EB-625FBE52EBFB}</UniqueIdentifier>
|
||||
<Extensions>h;hh;hpp;hxx;h++;hm;inl;inc;ipp;xsd</Extensions>
|
||||
</Filter>
|
||||
<Filter Include="资源文件">
|
||||
<UniqueIdentifier>{67DA6AB6-F800-4c08-8B7A-83BB121AAD01}</UniqueIdentifier>
|
||||
<Extensions>rc;ico;cur;bmp;dlg;rc2;rct;bin;rgs;gif;jpg;jpeg;jpe;resx;tiff;tif;png;wav;mfcribbon-ms</Extensions>
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</Filter>
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</ItemGroup>
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<ItemGroup>
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<None Include="Sqrt0001.asm">
|
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<Filter>源文件</Filter>
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</None>
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</ItemGroup>
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</Project>
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@@ -0,0 +1,4 @@
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<?xml version="1.0" encoding="utf-8"?>
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<Project ToolsVersion="Current" xmlns="http://schemas.microsoft.com/developer/msbuild/2003">
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<PropertyGroup />
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</Project>
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@@ -0,0 +1,15 @@
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||||
.386 ; 编译器指令，使用386指令集
|
||||
.model flat, stdcall ; model汇编指令，程序的内存模式, flat是windows程序，没有远近指针，stdcall是windows函数用的参数方式，即参数从右向左传递
|
||||
option casemap :none ; 标签是否区分大小写
|
||||
include \masm32\include\windows.inc ; 包含了Win32 API 的一些常量和函数定义
|
||||
include \masm32\include\kernel32.inc ; 包含了后面使用的ExitProcess函数
|
||||
include \masm32\include\masm32.inc ; 包含了后面使用的StdOut函数，不是标准的Win32函数，由MASM提供
|
||||
includelib \masm32\lib\kernel32.lib ; 库文件
|
||||
includelib \masm32\lib\masm32.lib
|
||||
.data
|
||||
HelloWorld db "Hello World!", 0 ; 定义使用的字符串常量,db代表define byte。最后跟一个NUL，表示ANSI字符集结束符
|
||||
.code ; 开始代码区
|
||||
start: ; 所有的代码要在start标签后、end start前
|
||||
invoke StdOut, addr HelloWorld ; 调用函数StdOut，参数量HelloWorld的地址。注意StdOut是MASM提供的宏。其它编辑器里可以使用WriteConsole之类win32函数代替。
|
||||
invoke ExitProcess, 0 ; 调用ExitProcess
|
||||
end start
|
||||
@@ -0,0 +1,11 @@
|
||||
<?xml version="1.0" encoding="utf-8"?>
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<Project>
|
||||
<ProjectOutputs>
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||||
<ProjectOutput>
|
||||
<FullPath>D:\NitloadIndustry\研究项目\1-Flagship\TH2020\ProjectFile\Math\Asm\AsmMath\x64\Debug\AsmMath.exe</FullPath>
|
||||
</ProjectOutput>
|
||||
</ProjectOutputs>
|
||||
<ContentFiles />
|
||||
<SatelliteDlls />
|
||||
<NonRecipeFileRefs />
|
||||
</Project>
|
||||
@@ -0,0 +1 @@
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||||
|
||||
@@ -0,0 +1,2 @@
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||||
PlatformToolSet=v143:VCToolArchitecture=Native64Bit:VCToolsVersion=14.33.31629:TargetPlatformVersion=10.0.19041.0:
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Debug|x64|D:\NitloadIndustry\研究项目\1-Flagship\TH2020\ProjectFile\Math\Asm\AsmMath\|
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@@ -0,0 +1 @@
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x64\Debug\\_IsIncrementalBuild
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||||
BIN
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BIN
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@@ -0,0 +1,31 @@
|
||||
|
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Microsoft Visual Studio Solution File, Format Version 12.00
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# Visual Studio Version 17
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VisualStudioVersion = 17.3.32825.248
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MinimumVisualStudioVersion = 10.0.40219.1
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Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "Project1", "Project1\Project1.vcxproj", "{9C0FD617-CD38-48B5-A16C-909FBA56BBF5}"
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EndProject
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Global
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GlobalSection(SolutionConfigurationPlatforms) = preSolution
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Debug|x64 = Debug|x64
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Debug|x86 = Debug|x86
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Release|x64 = Release|x64
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Release|x86 = Release|x86
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EndGlobalSection
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GlobalSection(ProjectConfigurationPlatforms) = postSolution
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{9C0FD617-CD38-48B5-A16C-909FBA56BBF5}.Debug|x64.ActiveCfg = Debug|x64
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{9C0FD617-CD38-48B5-A16C-909FBA56BBF5}.Debug|x64.Build.0 = Debug|x64
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{9C0FD617-CD38-48B5-A16C-909FBA56BBF5}.Debug|x86.ActiveCfg = Debug|Win32
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{9C0FD617-CD38-48B5-A16C-909FBA56BBF5}.Debug|x86.Build.0 = Debug|Win32
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{9C0FD617-CD38-48B5-A16C-909FBA56BBF5}.Release|x64.ActiveCfg = Release|x64
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{9C0FD617-CD38-48B5-A16C-909FBA56BBF5}.Release|x64.Build.0 = Release|x64
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{9C0FD617-CD38-48B5-A16C-909FBA56BBF5}.Release|x86.ActiveCfg = Release|Win32
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{9C0FD617-CD38-48B5-A16C-909FBA56BBF5}.Release|x86.Build.0 = Release|Win32
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EndGlobalSection
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GlobalSection(SolutionProperties) = preSolution
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HideSolutionNode = FALSE
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EndGlobalSection
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GlobalSection(ExtensibilityGlobals) = postSolution
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SolutionGuid = {307D7E9C-13AC-4921-9291-5A74E0C07738}
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EndGlobalSection
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EndGlobal
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@@ -0,0 +1,31 @@
|
||||
#include <xmmintrin.h>
|
||||
#include <immintrin.h>
|
||||
#include <intrin.h>
|
||||
#include <stdio.h>
|
||||
|
||||
void main()
|
||||
{
|
||||
float a = sseSqrt(4.0f);
|
||||
|
||||
int b = (int)a;
|
||||
|
||||
printf(b);
|
||||
}
|
||||
|
||||
|
||||
float sseSqrt(float x)
|
||||
{
|
||||
|
||||
float* pa = &x;
|
||||
float result[4];
|
||||
|
||||
__m128 b;
|
||||
|
||||
b = _mm_load_ss(pa);
|
||||
|
||||
__m128 c = _mm_sqrt_ss(b);
|
||||
|
||||
_mm_store_ss(result, c);
|
||||
|
||||
return result[3];
|
||||
}
|
||||
@@ -0,0 +1,135 @@
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<?xml version="1.0" encoding="utf-8"?>
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<ProjectConfiguration Include="Debug|Win32">
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<Configuration>Debug</Configuration>
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<Platform>Win32</Platform>
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</ProjectConfiguration>
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<ProjectConfiguration Include="Release|Win32">
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<Configuration>Release</Configuration>
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<Platform>Win32</Platform>
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</ProjectConfiguration>
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<ProjectConfiguration Include="Debug|x64">
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<Configuration>Debug</Configuration>
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<Platform>x64</Platform>
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</ProjectConfiguration>
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<ProjectConfiguration Include="Release|x64">
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<Configuration>Release</Configuration>
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<Keyword>Win32Proj</Keyword>
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<ProjectGuid>{9c0fd617-cd38-48b5-a16c-909fba56bbf5}</ProjectGuid>
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<RootNamespace>Project1</RootNamespace>
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||||
AsmSqrt.c
|
||||
D:\NitloadIndustry\研究项目\1-Flagship\TH2020\ProjectFile\Math\C\Project1\Project1\AsmSqrt.c(8,12): warning C4013: “sseSqrt”未定义；假设外部返回 int
|
||||
D:\NitloadIndustry\研究项目\1-Flagship\TH2020\ProjectFile\Math\C\Project1\Project1\AsmSqrt.c(12,10): warning C4047: “函数”:“const char *const ”与“int”的间接级别不同
|
||||
D:\NitloadIndustry\研究项目\1-Flagship\TH2020\ProjectFile\Math\C\Project1\Project1\AsmSqrt.c(12,9): warning C4024: “printf”: 形参和实参 1 的类型不同
|
||||
D:\NitloadIndustry\研究项目\1-Flagship\TH2020\ProjectFile\Math\C\Project1\Project1\AsmSqrt.c(8,12): warning C4244: “初始化”: 从“int”转换到“float”，可能丢失数据
|
||||
D:\NitloadIndustry\研究项目\1-Flagship\TH2020\ProjectFile\Math\C\Project1\Project1\AsmSqrt.c(17,1): warning C4142: "sseSqrt": 类型的良性重定义
|
||||
MSVCRTD.lib(exe_main.obj) : error LNK2019: 无法解析的外部符号 main，函数 "int __cdecl invoke_main(void)" (?invoke_main@@YAHXZ) 中引用了该符号
|
||||
D:\NitloadIndustry\研究项目\1-Flagship\TH2020\ProjectFile\Math\C\Project1\x64\Debug\Project1.exe : fatal error LNK1120: 1 个无法解析的外部命令
|
||||
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PlatformToolSet=v143:VCToolArchitecture=Native64Bit:VCToolsVersion=14.33.31629:TargetPlatformVersion=10.0.19041.0:
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{ "notes": [
|
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{ "note_name": "round_note", "note_value":"<br />Rounding is done according to the \"rounding[3:0]\" parameter, which can be one of:<div class='desc_note'> (_MM_FROUND_TO_NEAREST_INT |_MM_FROUND_NO_EXC) // round to nearest, and suppress exceptions\n (_MM_FROUND_TO_NEG_INF |_MM_FROUND_NO_EXC) // round down, and suppress exceptions\n (_MM_FROUND_TO_POS_INF |_MM_FROUND_NO_EXC) // round up, and suppress exceptions\n (_MM_FROUND_TO_ZERO |_MM_FROUND_NO_EXC) // truncate, and suppress exceptions\n _MM_FROUND_CUR_DIRECTION // use MXCSR.RC; see _MM_SET_ROUNDING_MODE</div>"},
|
||||
{ "note_name": "sae_note", "note_value":"<br />Exceptions can be suppressed by passing \"_MM_FROUND_NO_EXC\" in the \"sae\" parameter."},
|
||||
{ "note_name": "round_imm_note", "note_value":"<br />Rounding is done according to the \"imm8[2:0]\" parameter, which can be one of:<div class='desc_note'> _MM_FROUND_TO_NEAREST_INT // round to nearest\n _MM_FROUND_TO_NEG_INF // round down\n _MM_FROUND_TO_POS_INF // round up\n _MM_FROUND_TO_ZERO // truncate\n _MM_FROUND_CUR_DIRECTION // use MXCSR.RC; see _MM_SET_ROUNDING_MODE</div>"},
|
||||
{ "note_name": "round2_note", "note_value":"<br />Rounding is done according to the \"rounding[3:0]\" parameter, which can be one of:<div class='desc_note'> (_MM_FROUND_TO_NEAREST_INT) // round to nearest\n (_MM_FROUND_TO_NEG_INF) // round down\n (_MM_FROUND_TO_POS_INFC) // round up\n (_MM_FROUND_TO_ZERO) // truncate\n _MM_FROUND_CUR_DIRECTION // use MXCSR.RC; see _MM_SET_ROUNDING_MODE\n (_MM_FROUND_TO_NEAREST_INT |_MM_FROUND_NO_EXC) // round to nearest, and suppress exceptions\n (_MM_FROUND_TO_NEG_INF |_MM_FROUND_NO_EXC) // round down, and suppress exceptions\n (_MM_FROUND_TO_POS_INF |_MM_FROUND_NO_EXC) // round up, and suppress exceptions\n (_MM_FROUND_TO_ZERO |_MM_FROUND_NO_EXC) // truncate, and suppress exceptions\n (_MM_FROUND_CUR_DIRECTION |_MM_FROUND_NO_EXC) // use MXCSR.RC and suppress exceptions; see _MM_SET_ROUNDING_MODE</div>"},
|
||||
{ "note_name": "strcmp_note", "note_value":"<br />\"imm\" can be a combination of:<div class='desc_note'> _SIDD_UBYTE_OPS // unsigned 8-bit characters\n _SIDD_UWORD_OPS // unsigned 16-bit characters\n _SIDD_SBYTE_OPS // signed 8-bit characters\n _SIDD_SWORD_OPS // signed 16-bit characters\n _SIDD_CMP_EQUAL_ANY // compare equal any\n _SIDD_CMP_RANGES // compare ranges\n _SIDD_CMP_EQUAL_EACH // compare equal each\n _SIDD_CMP_EQUAL_ORDERED // compare equal ordered\n _SIDD_NEGATIVE_POLARITY // negate results\n _SIDD_MASKED_NEGATIVE_POLARITY // negate results only before end of string\n _SIDD_LEAST_SIGNIFICANT // index only: return last significant bit\n _SIDD_MOST_SIGNIFICANT // index only: return most significant bit\n _SIDD_BIT_MASK // mask only: return bit mask\n _SIDD_UNIT_MASK // mask only: return byte/word mask</div>"},
|
||||
{ "note_name": "getmant_note", "note_value":"<br />The mantissa is normalized to the interval specified by \"interv\", which can take the following values:<div class='desc_note'> _MM_MANT_NORM_1_2 // interval [1, 2)\n _MM_MANT_NORM_p5_2 // interval [0.5, 2)\n _MM_MANT_NORM_p5_1 // interval [0.5, 1)\n _MM_MANT_NORM_p75_1p5 // interval [0.75, 1.5)</div>The sign is determined by \"sc\" which can take the following values:<div class='desc_note'> _MM_MANT_SIGN_src // sign = sign(src)\n _MM_MANT_SIGN_zero // sign = 0\n _MM_MANT_SIGN_nan // dst = NaN if sign(src) = 1</div>"},
|
||||
{ "note_name": "fpclass_note", "note_value":"<br />\"imm\" can be a combination of:<div class='desc_note'> 0x01 // QNaN\n 0x02 // Positive Zero\n 0x04 // Negative Zero\n 0x08 // Positive Infinity\n 0x10 // Negative Infinity\n 0x20 // Denormal\n 0x40 // Negative\n 0x80 // SNaN</div>"},
|
||||
{ "note_name": "max_float_note", "note_value":"<br />\"dst\" is not following IEEE 754 maximum when inputs are nan or signed-zero values."},
|
||||
{ "note_name": "min_float_note", "note_value":"<br />\"dst\" is not following IEEE 754 minimum when inputs are nan or signed-zero values."}
|
||||
]}
|
||||
@@ -0,0 +1,38 @@
|
||||
<!doctype html>
|
||||
<html>
|
||||
<head>
|
||||
<meta http-equiv='X-UA-Compatible' content='IE=9; IE=8; IE=7; IE=EDGE' />
|
||||
<title>Intel® Intrinsics Guide</title>
|
||||
<link rel='shortcut icon' href='favicon.ico' />
|
||||
<link type='text/css' rel='stylesheet' href='style.min.css' />
|
||||
<link type='text/css' rel='stylesheet' href='style-offline.min.css' />
|
||||
</head>
|
||||
<body>
|
||||
<div id='ig_container'>
|
||||
<div style='margin:0px;padding:15px 20px;'>
|
||||
<div>
|
||||
<div id='title'><b>Intel® Intrinsics Guide</b></div>
|
||||
<div style='clear:both;'></div>
|
||||
</div>
|
||||
<div>
|
||||
<h2>Third Party Library Attributions</h2>
|
||||
|
||||
This site uses the <a href="https://www.jquery.com">jQuery*</a> library for interactive search and filtering of content.
|
||||
|
||||
jQuery is release under the <a href="https://tldrlegal.com/license/mit-license">MIT license</a>.
|
||||
</div>
|
||||
<div>
|
||||
<h2>Notices and Disclaimers</h2>
|
||||
<p>Intel technologies may require enabled hardware, software or service activation.</p>
|
||||
<p>No product or component can be absolutely secure.</p>
|
||||
<p>Your costs and results may vary.</p>
|
||||
<p>© Intel Corporation. Intel, the Intel logo, and other Intel marks are trademarks of Intel Corporation or its subsidiaries.</p>
|
||||
<p>*Other names and brands may be claimed as the property of others.</p>
|
||||
<p>No license (express or implied, by estoppel or otherwise) to any intellectual property rights is granted by this document.</p>
|
||||
<p>The products described may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request.</p>
|
||||
<p>Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade.</p>
|
||||
</div>
|
||||
</div>
|
||||
</div>
|
||||
</body>
|
||||
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||||
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|
||||
<!doctype html>
|
||||
<html>
|
||||
<head>
|
||||
<meta http-equiv='X-UA-Compatible' content='IE=9; IE=8; IE=7; IE=EDGE' />
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||||
<title>Intel® Intrinsics Guide</title>
|
||||
<link rel='shortcut icon' href='favicon.ico' />
|
||||
<link type='text/css' rel='stylesheet' href='style.min.css' />
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||||
<link type='text/css' rel='stylesheet' href='style-offline.min.css' />
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||||
<body>
|
||||
<div id='ig_body'>
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||||
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||||
<div style='margin:0px;padding:15px 20px;'>
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||||
<div id='ig_title'>
|
||||
<div id='title'>
|
||||
<b>Intel® Intrinsics Guide</b>
|
||||
</div>
|
||||
<div style='clear:both;'></div>
|
||||
</div>
|
||||
<section>
|
||||
<h2>Release Notes</h2>
|
||||
<h3>3.6.5 Release</h3>01/24/2023
|
||||
<ul>
|
||||
<li>Added 64 reduce_*_ep* series intrinsics.</li>
|
||||
<li>Corrected parameter order of _mm_test_all_zeros and _mm_test_mix_ones_zeros.</li>
|
||||
<li>Add new throughput and latency data for Sapphire Rapids.</li>
|
||||
</ul>
|
||||
|
||||
<h3>3.6.4 Release</h3>12/14/2022
|
||||
<ul>
|
||||
<li>Added SVML intrinsics for AVX512_FP16.</li>
|
||||
<li>Added intrinsics for:
|
||||
<ul>
|
||||
<li>AMX-FP16</li>
|
||||
<li>AVX_IFMA</li>
|
||||
<li>AVX_NE_CONVERT</li>
|
||||
<li>AVX_VNNI_INT8</li>
|
||||
<li>CMPCCXADD</li>
|
||||
<li>PREFETCHI</li>
|
||||
<li>RAO_INT</li>
|
||||
</ul>
|
||||
</li>
|
||||
<li>Added 9 new AMX intrinsics: __tile_*.
|
||||
<li>Refined description of _mm_cvtsbh_ss and *_cvtpbh_ps.
|
||||
<li>Fixed Instruction of _mm_mask3_fmadd_(round)_sch.</li>
|
||||
<li>Corrected _mm256_cvtps_ph/_mm_cvtps_ph's parameter name and description.</li>
|
||||
<li>Extended _mm512_(mask/z)_cvt_roundps_ph, _mm512_(mask/z)_cvtps_ph's rounding and SAE control.</li>
|
||||
<li>Corrected _tile_load/storeconfig's operation.</li>
|
||||
<li>Corrected stride type of AMX intrinsics.
|
||||
</ul>
|
||||
<h3>3.6.3 Release</h3>08/10/2022
|
||||
<ul>
|
||||
<li>Removed legacy throughput and latency data for Knights Landing, Ivy Bridge, Haswell, and Broadwell.</li>
|
||||
<li>Added new throughput and latency data for Icelake Intel Core, Icelake Xeon, and Alderlake.</li>
|
||||
<li>Updated the header information for CPUID FP16C from emmintrin.h to immintrin.h.</li>
|
||||
<li>Corrected the operation example for _mm_ucomineq_sh and _mm_comineq_sh.</li>
|
||||
</ul>
|
||||
<h3>3.6.2 Release</h3>04/22/2022
|
||||
<ul>
|
||||
<li>Added 1 intrinsic for BMI: _tzcnt_u16.</li>
|
||||
<li>Added a new tag <supported> to mark intrinsics' compiler support.</li>
|
||||
<li>Added helper enum for ternary intrinsics.</li>
|
||||
<li>Changed CPUID of _mm_(loadu/storeu)_si(16/64) from SSE to SSE2.</li>
|
||||
<li>Added new CPUID CRC32 for _mm_crc32_u(8/16/32/64) intrinsics.</li>
|
||||
<li>Corrected formatting error for _mm_div_ps and _mm_div_ss performance latency data (Ivy Bridge).</li>
|
||||
</ul>
|
||||
<h2>Release Notes</h2>
|
||||
<h3>3.6.1 Release</h3>12/06/2021
|
||||
<ul>
|
||||
<li>Corrected operation description for _mm_encodekey256_u32: Change handle size of encodekey256 from 384 to 512.</li>
|
||||
<li> Added seven intrinsics for AVX512_FP16: _mm_mask3_fcmadd_(round_)sch, _mm_mask3_fmadd_(round_)sch, _mm(256, 512)_set1_pch.</li>
|
||||
<li> Fixed part of KNCNI intrinsic CPUID flag.</li>
|
||||
<li> Corrected description for _mm256_hsub_ps.</li>
|
||||
<li> Corrected categories for *_shuffle_epi8.</li>
|
||||
<li> Improved description of AVX512_FP16 *_min/max_* intrinsics.</li>
|
||||
<li> Improved operation description of AVX512_FP16 *_comi_* intrinsics.</li>
|
||||
<li> Added 11 intrinsics for AVX512_BF16: _mm(256/512)_(mask/maskz)_cvtpbh_ps, _mm_cvtsbh_ss, _mm_cvtness_sbh.</li>
|
||||
<li> Added 36 intrinsics alias for AVX512_FP16: *_mul_*ch alias for *_f*mul_*ch.</li>
|
||||
</ul>
|
||||
<h2>Release Notes</h2>
|
||||
<h3>3.6.0 Release</h3>06/30/2021
|
||||
<ul>
|
||||
<li>Added intrinsics for AVX512_FP16, ENQCMD, AVX_VNNI, HRESET, KEYLOCKER, KEYLOCKER_WIDE and UINTR.</li>
|
||||
<li>Added two intrinsics for AVX512F: _mm512_(mask_)i32loscatter_epi64.</li>
|
||||
<li>Improved description for WAITPKG intrinsics.</li>
|
||||
<li>Improved operation for *_reduce_* intrinsics.</li>
|
||||
<li>Improved description for *_min/max_* float intrinsics.</li>
|
||||
<li>Improved operation for *_comi_* intrinsics.</li>
|
||||
<li>Updated XML format: removed <type> tag; reordered the tags and attributes.</li>
|
||||
<li>Shared CPUID intrinsics now will be listed as two separate items.</li>
|
||||
<li>Updated notices and disclaimers.</li>
|
||||
<li>Update introduction with links to supporting documentation.</li>
|
||||
<li>Updated fonts to use web-safe font stack.</li>
|
||||
</ul>
|
||||
<h3>3.5.4 Release</h3>10/19/2020
|
||||
<ul>
|
||||
<li>Fixed a recurring typo ("Seqeuence" --> "Sequence").</li>
|
||||
</ul>
|
||||
<h3>3.5.3 Release</h3>06/30/2020
|
||||
<ul>
|
||||
<li>Added intrinsics for AMX-TILE, AMX-BF16, and AMX-INT8.</li>
|
||||
</ul>
|
||||
<h3>3.5.2 Release</h3>06/05/2020
|
||||
<ul>
|
||||
<li>Added intrinsics for SERIALIZE and TSXLDTRK.</li>
|
||||
<li>Improved indication of intrinsics that are sequences of instructions.</li>
|
||||
<li>Improved presentation of long lines in operations.</li>
|
||||
</ul>
|
||||
<h3>3.5.1 Release</h3>05/22/2020
|
||||
<ul>
|
||||
<li>Updated latency and throughput data for Skylake.</li>
|
||||
<li>Resolved an issue preventing intrinsics from loading.</li>
|
||||
</ul>
|
||||
<h3>3.5.0 Release</h3>03/16/2020
|
||||
<ul>
|
||||
<li>Added latency and throughput data for 10th gen Intel® Core™ processor family (Icelake).</li>
|
||||
<li>Updated XML format: added a <return> tag for the return type and removed the rettype attribute; added several attributes to <return> and <parameter>; added XED iform attribute to <instruction>.</li>
|
||||
<li>Added instruction forms for many AVX512 intrinsics.</li>
|
||||
<li>Clarified embedded-rounding vs suppress-all-exceptions distinction for many intrinsics.</li>
|
||||
<li>Clarified masking operands in instruction forms.</li>
|
||||
<li>Corrected operation for all AVX512_VNNI and GFNI intrinsics.</li>
|
||||
<li>Clarified immediate bit-range access in many operations.</li>
|
||||
<li>Corrected destination zeroing for many store intrinsics.</li>
|
||||
<li>Clarified operator precedence for many intrinsic operations.</li>
|
||||
<li>Clarified indication of signed integers in many descriptions.</li>
|
||||
<li>Corrected scalar upper pass through variable for many intrinsics.</li>
|
||||
<li>Clarified memory accesses for many intrinsics.</li>
|
||||
<li>Added CPUID for CET_SS intrinsics.</li>
|
||||
<li>Corrected operations for many scatter and gather intrinsics.</li>
|
||||
<li>Corrected descriptions and operations for SVML intrinsics involving complex numbers.</li>
|
||||
<li>Corrected operation for _mm512_set_epi8.</li>
|
||||
<li>Corrected description for several *_set_epi* intrinsics.</li>
|
||||
<li>Corrected instruction for some *_xor_* intrinsics.</li>
|
||||
<li>Corrected description and operation for *_ktestc_* and *_kortestc_* intrinsics.</li>
|
||||
<li>Corrected operation for several *_permutex2var_* intrinsics.</li>
|
||||
<li>Clarified imm8 bit ranges for _alignr_ intrinsics.</li>
|
||||
<li>Corrected write mask pass through for some broadcast_i* and broadcast_f* intrinsics.</li>
|
||||
<li>Corrected imm8 bit range for some shuffle_i* intrinsics.</li>
|
||||
<li>Corrected operation for _kor_* intrinsics.</li>
|
||||
<li>Corrected operations for unmasked _movedup_ intrinsics.</li>
|
||||
<li>Corrected operations for *_set4_* and *_setr4_* intrinsics.</li>
|
||||
<li>Clarified imm8 bit range for _kshiftri_mask16.</li>
|
||||
<li>Corrected parameter types for *_4fmadd_ps intrinsics.</li>
|
||||
<li>Corrected operation for _mm256_mpsadbw_epu8.</li>
|
||||
<li>Corrected operations for *_maskz_mulhrs_epi16 intrinsics.</li>
|
||||
<li>Corrected operations for *_hadds_* intrinsics.</li>
|
||||
<li>Corrected saturation function for *_cvtusepi* intrinsics.</li>
|
||||
<li>Corrected shift direction for some *_srai_* intrinsics.</li>
|
||||
<li>Corrected operation for _mm256_mask_srlv_epi16.</li>
|
||||
<li>Corrected operation for _mm512_reduce_max_epi64.</li>
|
||||
<li>Corrected operations for _mm512_mask_permute4f128_* intrinsics.</li>
|
||||
<li>Corrected operations for _mm_tzcnti_* intrinsics.</li>
|
||||
<li>Corrected operations for several *_cvtt_* intrinsics.</li>
|
||||
<li>Corrected operations for several scalar conversion intrinsics.</li>
|
||||
<li>Corrected operations for several *_exp2a23_* intrinsics.</li>
|
||||
<li>Corrected operations for several intrinsics with single-precision reciprocals.</li>
|
||||
<li>Corrected operations for *_fmadd_ps intrinsics.</li>
|
||||
<li>Corrected operation for _mm_cvttss_si64.</li>
|
||||
<li>Corrected comparison operator for several cmpgt and cmplt intrinsics.</li>
|
||||
<li>Corrected operations for several right rotation intrinsics.</li>
|
||||
<li>Corrected operation for _mm_ceil_pd.</li>
|
||||
<li>Corrected operation for _mm512_mask_floor_ps.</li>
|
||||
<li>Corrected operations for several loadu intrinsics.</li>
|
||||
<li>Corrected src parameter for _mask_exp2a23_ intrinsics.</li>
|
||||
</ul>
|
||||
<h3>3.4.7 Release</h3>07/15/2019
|
||||
<ul>
|
||||
<li>Corrected operations for add/sub and sub/add intrinsics.</li>
|
||||
<li>Corrected operations for GFNI affine intrinsics.</li>
|
||||
<li>Corrected operations for dpbf16 intrinsics.</li>
|
||||
</ul>
|
||||
<h3>3.4.6 Release</h3>07/15/2019
|
||||
<ul>
|
||||
<li>Added intrinsics for AVX512_VP2INTERSECT.</li>
|
||||
</ul>
|
||||
<h3>3.4.5 Release</h3>05/30/2019
|
||||
<ul>
|
||||
<li>Added additional latency & throughput data for AVX-512 instructions.</li>
|
||||
<li>Improvements to operations for most intrinsics.</li>
|
||||
<li>Corrections to operations for many intrinsics, including AVX512_BITALG and AVX512_VNNI.</li>
|
||||
</ul>
|
||||
<h3>3.4.4 Release</h3>04/17/2019
|
||||
<ul>
|
||||
<li>Added BF16 intrinsics.</li>
|
||||
<li>Corrected operations for *_reduce_ps/pd intrinsics.</li>
|
||||
<li>Corrected operations for non-mask sllv_epi16 intrinsics.</li>
|
||||
</ul>
|
||||
<h3>3.4.3 Release</h3>04/08/2019
|
||||
<ul>
|
||||
<li>Improved operation syntax for many intrinsics.</li>
|
||||
<li>Corrected parameters for several cmp intrinsics.</li>
|
||||
<li>Corrected details of _mm512[_mask]_log2_ps.</li>
|
||||
<li>Corrected operations for: _mm_cvtpd_ps, _m_pmaddwd, *_madd_epi16, *_maskz_sub_epi8, *_maskz_sub_epi16.</li>
|
||||
<li>Corrected instructions for _mm_comi_round_ss.</li>
|
||||
<li>Corrected description and operation for _lrot*,.</li>
|
||||
<li>Corrected instructions and descriptions and operation _tpause and _umwait.</li>
|
||||
</ul>
|
||||
<h3>3.4.2 Release</h3>10/05/2018
|
||||
<ul>
|
||||
<li>Added intrinsics for AVX512_BITALG, AVX512_VBMI2, AVX512_VNNI, GFNI, VAES, VPCLMULQDQ, and others.</li>
|
||||
<li>Corrected CPUID and description for load/storebe intrinsics.</li>
|
||||
<li>Corrected operation for _mm_mask_4fmadd_ss.</li>
|
||||
<li>Corrected description for _mm_srli_epi32.</li>
|
||||
<li>Corrected description for _mm_alignr_pi8.</li>
|
||||
<li>Corrected description and operation for _xtest.</li>
|
||||
</ul>
|
||||
<h3>3.4.1 Release</h3>04/26/2018
|
||||
<ul>
|
||||
<li>Added ptwrite and encl* intrinsics.</li>
|
||||
<li>Corrected description and operation for blend intrinsics with an immediate control.</li>
|
||||
<li>Corrected CPUID for _mm512_4fmadd_ps.</li>
|
||||
<li>Corrected description for masked compare intrinsics.</li>
|
||||
<li>Clarified that includes should use <header.h> rather than "header.h".</li>
|
||||
<li>Corrected operations for _mm512_kunpack* intrinsics.</li>
|
||||
<li>Further clarified up and down conversion for intrinsics supported on both KNC and AVX-512.</li>
|
||||
<li>Corrected return type for 4dpwssd* intrinsics.</li>
|
||||
<li>Corrected description and operation for scalar mask3 intrinsics.</li>
|
||||
</ul>
|
||||
<h3>3.4 Release</h3>09/07/2017
|
||||
<ul>
|
||||
<li>Added intrinsics for Knights Mill (KNM).</li>
|
||||
<li>Corrected references to "_MM_CMPINT_NE".</li>
|
||||
<li>Corrected instruction for _mm512_stream_si512.</li>
|
||||
<li>Corrected CPUID for _mm256_extract_epi8, _mm256_extract_epi16, _mm[256,512]_cvt[ss,sd,si256,si512].</li>
|
||||
<li>Improved description of _xbegin.</li>
|
||||
<li>Clarified up and down conversion for intrinsics supported on both KNC and AVX-512.</li>
|
||||
<li>Corrected description of _mm_countbits_64.</li>
|
||||
</ul>
|
||||
<h3>3.3.16 Release</h3>01/26/2017
|
||||
<ul>
|
||||
<li>Added additional latency & throughput data up through 6th generation Intel® Core™ processor family (Skylake) and 2nd Generation Intel® Xeon Phi™ (Knights Landing).</li>
|
||||
<li>Added documentation on 36 intrinsics.</li>
|
||||
<li>Corrected operations for vsqrtss intrinsics.</li>
|
||||
<li>Corrected movd CPUID bits.</li>
|
||||
</ul>
|
||||
<h3>3.3.15 Release</h3>09/16/2016
|
||||
<ul>
|
||||
<li>Corrected operation for _mm_mpsadbw_epu8.</li>
|
||||
<li>Corrected latency and throughput data for FP16C intrinsics.</li>
|
||||
<li>Corrected operations for *_madd_epi16 intrinsics.</li>
|
||||
<li>Corrected operations for _subborrow_u* intrinsics.</li>
|
||||
<li>Corrected instruction forms for *_i32gather_* and *_i64gather_* intrinsics.</li>
|
||||
<li>Corrected operations *_i64gather_* intrinsics.</li>
|
||||
<li>Corrected operation for _mm256_shuffle_epi8.</li>
|
||||
<li>Corrected operations for _mm512_shuffle_epi8, _mm512_mask_shuffle_epi8, _mm512_maskz_shuffle_epi8, _mm256_mask_shuffle_epi8, _mm256_maskz_shuffle_epi8.</li>
|
||||
<li>Corrected descriptions and operations for *_sqrt_sd and *_sqrt_round_sd intrinsics.</li>
|
||||
<li>Corrected operations for _mm512_mask2int intrinsics.</li>
|
||||
<li>Corrected CPUIDs for _mm_undefined_* intrinsics.</li>
|
||||
</ul>
|
||||
<h3>3.3.14 Release</h3>01/12/2016
|
||||
<ul>
|
||||
<li>Corrected operations for *_cmpunord_* intrinsics.</li>
|
||||
</ul>
|
||||
<h3>3.3.13 Release</h3>12/02/2015
|
||||
<ul>
|
||||
<li>Clarified descriptions and operations for all intrinsics utilizing a bitwise AND NOT.</li>
|
||||
<li>Corrected description and operation for _mm512_fmadd233_ps and _mm512_mask_fmadd233_ps.</li>
|
||||
<li>Added AVX-512 versions of _mm512_mask2int and _mm512_int2mask.</li>
|
||||
</ul>
|
||||
<h3>3.3.12 Release</h3>09/28/2015
|
||||
<ul>
|
||||
<li>Corrected operations for multi-shift intrinsics.</li>
|
||||
<li>Corrected description and operation of _mm_test_all_ones.</li>
|
||||
<li>Corrected description for _mm512_sad_epu8.</li>
|
||||
<li>Corrected operation for _mm256_mpsadbw_epu8.</li>
|
||||
</ul>
|
||||
<h3>3.3.11 Release</h3>07/27/2015
|
||||
<ul>
|
||||
<li>Corrected operations for fmsubadd intrinsics.</li>
|
||||
</ul>
|
||||
<h3>3.3.10 Release</h3>06/24/2015
|
||||
<ul>
|
||||
<li>Corrected ADC, ADCX, and SBB intrinsics.</li>
|
||||
</ul>
|
||||
<h3>3.3.9 Release</h3>06/15/2015
|
||||
<ul>
|
||||
<li>Corrected operations for variable shift intrinsics.</li>
|
||||
</ul>
|
||||
<h3>3.3.8 Release</h3>05/26/2015
|
||||
<ul>
|
||||
<li>Corrected headers for all AVX-512 intrinsics.</li>
|
||||
</ul>
|
||||
<h3>3.3.7 Release</h3>02/20/2015
|
||||
<ul>
|
||||
<li>Corrected operations for _mm_sha1rnds4_epu32, _mm_sha1nexte_epu32, and _mm_sha1msg2_epu32.</li>
|
||||
</ul>
|
||||
<h3>3.3.6 Release</h3>02/02/2015
|
||||
<ul>
|
||||
<li>Corrected operations for floating-point hsub intrinsics.</li>
|
||||
</ul>
|
||||
<h3>3.3.5 Release</h3>01/29/2015
|
||||
<ul>
|
||||
<li>Added missing _BitScan*, _bittest*, _mm256_extract_epi*, _mm256_insert_epi*, and _mm_clflushopt intrinsics.</li>
|
||||
</ul>
|
||||
<h3>3.3.4 Release</h3>01/13/2015
|
||||
<ul>
|
||||
<li>Corrected parameter names, descriptions, and operations for intrinsics with immediate parameters, to clarify they are always 8-bits.</li>
|
||||
<li>Corrected description and operation for all pmaddwd intrinsics.</li>
|
||||
</ul>
|
||||
<h3>3.3.3 Release</h3>12/18/2014
|
||||
<ul>
|
||||
<li>Corrected description for _mm_maskmoveu_si128 and _mm_maskmove_si64.</li>
|
||||
<li>Corrected operation for _mm512_[mask_]extload_* intrinsics.</li>
|
||||
</ul>
|
||||
<h3>3.3.2 Release</h3>12/10/2014
|
||||
<ul>
|
||||
<li>Corrected description for vpmaksmov intrinsics.</li>
|
||||
<li>Corrected description for (v)pmaddwd intrinsics.</li>
|
||||
</ul>
|
||||
<h3>3.3.1 Release</h3>10/17/2014
|
||||
<ul>
|
||||
<li>Corrected category for *_mask_cmp_*_mask, *_test_*_mask, and *_testn_*_maks intrinsics.</li>
|
||||
<li>Corrected description and operation for *_testn_*_maks intrinsics.</li>
|
||||
<li>Added description and operation for _mm_testn_epi64_mask and _mm_test_epi64_mask.</li>
|
||||
<li>Corrected typos in description of several getexp, packs, div, and broadcast intrinsics.</li>
|
||||
<li>Corrected instructions for *_mask_permutex2var_* and *_mask2_permutex2var_* intrinsics.</li>
|
||||
<li>Corrected for CPUID's for 128-bit and 256-bit lzcnt and conflict intrinsics.</li>
|
||||
<li>Corrected description for all broadcastw and fpclass intrinsics.</li>
|
||||
</ul>
|
||||
<h3>3.3.0 Release</h3>09/29/2014
|
||||
<ul>
|
||||
<li>Added AVX-512IFMA52 and AVX-512VBMI intrinsics.</li>
|
||||
</ul>
|
||||
<h3>3.2.2 Release</h3>09/03/2014
|
||||
<ul>
|
||||
<li>Corrected _mm512_mask_permute4f128_epi32 operation.</li>
|
||||
</ul>
|
||||
<h3>3.2.1 Release</h3>07/24/2014
|
||||
<ul>
|
||||
<li>Corrected CPUIDs for _mm_broadcastmb_epi64, _mm256_broadcastmb_epi64, _mm_broadcastmw_epi32, _mm256_broadcastmw_epi32, and _mm_movm_epi8.</li>
|
||||
</ul>
|
||||
<h3>3.2.0 Release</h3>07/18/2014
|
||||
<ul>
|
||||
<li>Added AVX-512VL, AVX-512BW, and AVX-512DQ intrinsics.</li>
|
||||
</ul>
|
||||
<h3>3.1.9 Release</h3>06/18/2014
|
||||
<ul>
|
||||
<li>Re-classified all *_reduce_* intrinsics (except gmin and gmax) as both AVX-512 and KNC, which were previously classified as only AVX-512.</li>
|
||||
</ul>
|
||||
<h3>3.1.8 Release</h3>06/17/2014
|
||||
<ul>
|
||||
<li>Corrected instructions for _mm512_mask2int, _mm512_int2mask, _mm512_cvtfxpnt_round_adjustepi32_ps, _mm512_mask_mulhi_epu32, _mm512_mask_i32loscatter_epi64, _mm512_mask_subsetb_epi32, _mm_tzcnti_32, _mm_tzcnti_64, _mm_prefetch, _mm512_extload_*, and _mm512_mask_extload_*.</li>
|
||||
<li>Re-classified 58 intrinsics as just AVX-512, which were previously classified as both AVX-512 and KNC (primarily broadcast intrinsics, and those containing __m128 or __m256 types).</li>
|
||||
<li>Re-classified _mm512_log2_ps and _mm512_mask_log2_ps as KNC, which were previously classified as SVML.</li>
|
||||
<li>Corrected parameters for _mm512_mask_prefetch_i32gather_ps, and re-classified as both AVX-512 and KNC.</li>
|
||||
<li>Corrected description of _mm_sad_epu8.</li>
|
||||
<li>Added _mm512_mask_prefetch_i32extgather_ps.</li>
|
||||
<li>Added prefetchwt1 form of _mm_prefetch.</li>
|
||||
</ul>
|
||||
<h3>3.1.7 Release</h3>05/30/2014
|
||||
<ul>
|
||||
<li>Corrected instructions for _mm512_permute_pd, _mm512_permutevar_pd, and _mm512_permutevar_ps, which all use vpermilpx instructions rather than vpermpx.</li>
|
||||
<li>Corrected descriptions for _mm*_xor_si* intrinsics.</li>
|
||||
<li>Added missing _mm512_mask_prefetch_i32gather_ps intrinsic.</li>
|
||||
<li>Re-classified _mm512_abs_pd, _mm512_abs_ps, _mm512_mask_abs_pd, and _mm512_mask_abs_ps intrinsics as both AVX-512 and KNC, which were previously classified as only KNC.</li>
|
||||
<li>Switched to HTTPS.</li>
|
||||
</ul>
|
||||
<h3>3.1.6 Release</h3>03/21/2014
|
||||
<ul>
|
||||
<li>Corrected instructions for: _mm_sub_epi16, _mm512_cvtfxpnt_round_adjustps_epi32, _mm512_extpackstorelo_epi64, _mm512_mask_extpackstorelo_epi64, _mm512_extpackstorelo_pd, _mm512_mask_extpackstorelo_pd.</li>
|
||||
<li>Added xsavec, xsaves, and xrstors intrinsics.</li>
|
||||
</ul>
|
||||
<h3>3.1.5 Release</h3>03/18/2014
|
||||
<ul>
|
||||
<li>Re-classified 342 intrinsics as both AVX-512 and KNC, which were previously classified as only AVX-512.</li>
|
||||
<li>Added 18 missing KNC intrinsics, which previously existed in AVX-512 but have different intrinsic signatures or instructions encodings for KNC.</li>
|
||||
<li>Corrected fmadd233 intrinsic descriptions and operations.</li>
|
||||
<li>Corrected CPUID for VPTESTN* intrinsics to AVX512F.</li>
|
||||
</ul>
|
||||
<h3>3.1.4 Release</h3>02/12/2014
|
||||
<ul>
|
||||
<li>Corrected "hint" parameter description for prefetch scatter/gather intrinsics.</li>
|
||||
<li>Corrected _mm512_prefetch_i32extgather_ps, _mm512_mask_prefetch_i32extscatter_ps, and _mm512_prefetch_i32extscatter_ps intrinsic descriptions and operations.</li>
|
||||
</ul>
|
||||
<h3>3.1.3 Release</h3>02/06/2014
|
||||
<ul>
|
||||
<li>Added AVX512F version of kortestw intrinsics.</li>
|
||||
</ul>
|
||||
<h3>3.1.2 Release</h3>01/28/2014
|
||||
<ul>
|
||||
<li>Updated throughput on Haswell for vblendpd/ps, vblendvp/ps, and vmulpd/ps.</li>
|
||||
<li>Added performance data for _mm_alignr_epi8.</li>
|
||||
<li>Resolved issues in Internet Explorer 8 and 9.</li>
|
||||
<li>Added intro message.</li>
|
||||
</ul>
|
||||
<h3>3.1.1 Release</h3>12/19/2013
|
||||
<ul>
|
||||
<li>Fixed VEX-equivalent warning message.</li>
|
||||
</ul>
|
||||
<h3>3.1 Release</h3>12/18/2013
|
||||
<ul>
|
||||
<li>Added Knights Corner (KNC) intrinsics.</li>
|
||||
<li>Added 512-bit SVML intrinsics.</li>
|
||||
<li>Added instruction parameters for many intrinsics, including all AVX-512 intrinsics.</li>
|
||||
<li>Added instruction latencies for many intrinsics.</li>
|
||||
<li>Updated AVX-512 CPUID names.</li>
|
||||
<li>Added feature flags for AVX-512(F,ER,PF,CD), SHA, and MPX.</li>
|
||||
<li>Corrected descriptions, operations, parameters, and instructions for many intrinsics.</li>
|
||||
</ul>
|
||||
<h3>3.0.1 Release</h3>07/23/2013
|
||||
<ul>
|
||||
<li>Corrected operations for set and setr intrinsics.</li>
|
||||
</ul>
|
||||
<h3>3.0 Release</h3>07/17/2013
|
||||
<ul>
|
||||
<li>Added intrinsics for Intel® AVX-512, Intel® MPX, RDSEED, and ADX.</li>
|
||||
<li>Added additional latency & throughput data up through 4th generation Intel® Core™ processor family.</li>
|
||||
<li>Added 148 missing intrinsics, and corrected information for 96 intrinsics.</li>
|
||||
</ul>
|
||||
<h3>2.8.1 Release</h3>05/13/2013
|
||||
<ul>
|
||||
<li>Fixed description for _mm_move_ss.</li>
|
||||
<li>Fixed parameters for _mm_max_epu32.</li>
|
||||
<li>Replaced references of __int datatype with int.</li>
|
||||
</ul>
|
||||
<h3>2.8 Release</h3>02/06/2013
|
||||
<ul>
|
||||
<li>Updated descriptions and operations for all intrinsics.</li>
|
||||
<li>Added additional latency & throughput data up through 3rd generation Intel® Core™ processor family.</li>
|
||||
</ul>
|
||||
<h3>2.7 Release</h3>11/28/2012
|
||||
<ul>
|
||||
<li>Added intrinsics for SVML, BMI1, BMI2, FXSR, INVPCID, LZCNT, POPCNT, RDRAND, RDTSCP, RTM, TSC, XSAVE, XSAVEOPT.</li>
|
||||
<li>Added header and CPUID feature flag information for each intrinsic.</li>
|
||||
</ul>
|
||||
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|
||||
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|
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|
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|
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|
||||
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|
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|
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|
||||
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|
||||
<input type="checkbox"/>
|
||||
AVX-512 family
|
||||
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|
||||
<div id="avx512_techs" style="display:none;">
|
||||
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|
||||
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|
||||
AVX-512F
|
||||
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|
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<div class="AVX512BW avx512tech">
|
||||
<input type="checkbox"/>
|
||||
AVX-512BW
|
||||
</div>
|
||||
<div class="AVX512CD avx512tech">
|
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<input type="checkbox"/>
|
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AVX-512CD
|
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</div>
|
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<div class="AVX512DQ avx512tech">
|
||||
<input type="checkbox"/>
|
||||
AVX-512DQ
|
||||
</div>
|
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<div class="AVX512ER avx512tech">
|
||||
<input type="checkbox"/>
|
||||
AVX-512ER
|
||||
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|
||||
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|
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|
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|
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|
||||
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|
||||
AVX-512PF
|
||||
</div>
|
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|
||||
<input type="checkbox"/>
|
||||
AVX-512VL
|
||||
</div>
|
||||
<div class="AVX512VPOPCNTDQ avx512tech">
|
||||
<input type="checkbox"/>
|
||||
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|
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|
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|
||||
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|
||||
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|
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|
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AVX-512_4VNNIW
|
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|
||||
<input type="checkbox"/>
|
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|
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|
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|
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|
||||
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|
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|
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|
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|
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|
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|
||||
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|
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|
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|
||||
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|
||||
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|
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|
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|
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|
||||
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|
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|
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|
||||
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
SVML
|
||||
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|
||||
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|
||||
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|
||||
Other
|
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|
||||
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|
||||
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|
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|
||||
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|
||||
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|
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|
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Categories
|
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|
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|
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|
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|
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|
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|
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|
||||
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|
||||
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|
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Additional resources:
|
||||
<ul>
|
||||
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|
||||
<a href="https://software.intel.com/content/www/us/en/develop/documentation/cpp-compiler-developer-guide-and-reference/top/compiler-reference/intrinsics.html">
|
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Intel® C++ Compiler Classic Developer Guide and Reference
|
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|
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|
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|
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Intel® 64 and IA-32 Architectures Software Developer Manuals
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.
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|
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|
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|
||||
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|
||||
<div class="popbox sequence" style="width:250px;">
|
||||
This intrinsic generates a sequence of instructions, which may perform worse than a native instruction. Consider the performance impact of this intrinsic.
|
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|
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