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@@ -39,7 +39,6 @@ namespace StgSharp.HighPerformance.Memory
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private const int PredictionLeastAhead = 1024;
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private readonly CacheLineData* _data;
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private readonly EvictionArray* _eviction;
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private readonly CacheLineHead* _head;
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private readonly CacheLinePrediction* _prediction;
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@@ -57,12 +56,12 @@ namespace StgSharp.HighPerformance.Memory
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public L4()
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{
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// init order is fallow by align requirement of each component.
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nuint cacheSize = (nuint)Unsafe.SizeOf<CacheLineData>() * CacheLineCount; // SIMDID, no less than 16 byte bit
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nuint entrySize = (nuint)Unsafe.SizeOf<CacheLineHead>() * CacheLineCount; // 16 byte align
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nuint predictionSize = (nuint)Unsafe.SizeOf<CacheLinePrediction>() * PredictionCount; //16 byte align
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nuint cacheSize = ((nuint)Unsafe.SizeOf<CacheLineData>()) * CacheLineCount; // SIMDID, no less than 16 byte bit
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nuint entrySize = ((nuint)Unsafe.SizeOf<CacheLineHead>()) * CacheLineCount; // 16 byte align
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nuint predictionSize = ((nuint)Unsafe.SizeOf<CacheLinePrediction>()) * PredictionCount; //16 byte align
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nuint mapSize = (nuint)SwissTable.RequestedNativeMemorySize; // 16 byte align
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nuint rrpvSize = (nuint)Unsafe.SizeOf<EvictionArray>(); // 16 byte align
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nuint stackSize = (nuint)sizeof(int) * CacheLineCount; // int align
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nuint stackSize = ((nuint)sizeof(int)) * CacheLineCount; // int align
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// malloc all memory at once, and free at once in Dispose.
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// This is to avoid fragmentation and improve performance.
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@@ -85,7 +84,17 @@ namespace StgSharp.HighPerformance.Memory
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ptr += stackSize;
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}
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public IPrefetchPredict PrefetchPredict { get; set; }
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public IL4Predict PrefetchPredict { get; set; }
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[MethodImpl(MethodImplOptions.AggressiveInlining)]
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public void ContinueOnce(
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L4CacheLine line
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)
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{
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if (line.Address > 0) {
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_ = Interlocked.Decrement(ref _aheadCount);
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}
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}
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[System.Diagnostics.CodeAnalysis.SuppressMessage(
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"Design",
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@@ -108,11 +117,11 @@ namespace StgSharp.HighPerformance.Memory
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}
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[MethodImpl(MethodImplOptions.AggressiveInlining)]
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public CacheLine Map(
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nuint origin
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public L4CacheLine Map(
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nuint origin
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)
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{
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if (_aheadCount < PredictionLeastAhead)
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if ((_aheadCount < PredictionLeastAhead) && !PrefetchPredict.IsExhausted)
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{
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if (Interlocked.CompareExchange(ref _prefetching, 1, 0) == 0)
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{
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@@ -141,7 +150,7 @@ namespace StgSharp.HighPerformance.Memory
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(*_eviction)[entry->_id] = 0;
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_ = Interlocked.Increment(ref _activeCount);
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_ = Interlocked.Decrement(ref _aheadCount);
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return new CacheLine(entry->_address, ref _activeCount, ref entry->_refCount);
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return new L4CacheLine(entry->_address, ref _activeCount, ref entry->_refCount);
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} else
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{
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_ = Interlocked.Decrement(ref entry->_refCount);
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@@ -157,41 +166,6 @@ namespace StgSharp.HighPerformance.Memory
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nuint origin
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);
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public ref struct CacheLine : IDisposable
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{
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private ref int _activeCount;
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private ref int _refCount;
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private nuint _handle;
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internal CacheLine(
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nuint handle,
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ref int activeCount,
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ref int cacheRefCount
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)
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{
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_handle = handle;
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_refCount = ref cacheRefCount;
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_activeCount = ref activeCount;
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}
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[Obsolete("You should not create a CacheLineHandle outside a L4", true)]
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public CacheLine() { }
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public nuint Address => _handle;
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public void Dispose()
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{
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if (_handle == 0) {
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return;
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}
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_handle = 0;
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_ = Interlocked.Decrement(ref _activeCount);
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_ = Interlocked.Decrement(ref _refCount);
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}
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}
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private struct CacheLineData
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{
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@@ -200,4 +174,39 @@ namespace StgSharp.HighPerformance.Memory
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}
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}
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public ref struct L4CacheLine : IDisposable
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{
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private ref int _activeCount;
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private ref int _refCount;
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private nuint _handle;
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internal L4CacheLine(
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nuint handle,
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ref int activeCount,
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ref int cacheRefCount
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)
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{
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_handle = handle;
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_refCount = ref cacheRefCount;
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_activeCount = ref activeCount;
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}
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[Obsolete("You should not create a CacheLineHandle outside a L4", true)]
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public L4CacheLine() { }
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public readonly nuint Address => _handle;
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public void Dispose()
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{
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if (_handle == 0) {
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return;
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}
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_handle = 0;
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_ = Interlocked.Decrement(ref _activeCount);
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_ = Interlocked.Decrement(ref _refCount);
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}
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}
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}
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