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This commit is contained in:
Youmu Liu
2026-03-26 18:02:13 +08:00
parent d960d02972
commit 06e3aa119b
20 changed files with 198 additions and 169 deletions
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StgSharp.Common/HighPerformance/Memory/L4.Predict.cs
+33 -10
View File
@@ -33,9 +33,11 @@ using System.Threading.Tasks;
namespace StgSharp.HighPerformance.Memory
{
public interface IPrefetchPredict
public interface IL4Predict
{
bool IsExhausted { get; }
/// <summary>
/// Writes predicted cache line descriptors into <paramref name="node" />.
/// </summary>
@@ -43,17 +45,20 @@ namespace StgSharp.HighPerformance.Memory
/// Prediction output buffer.
/// </param>
/// <param name="count">
/// When this method returns, contains the number of valid entries written to <paramref
/// When this method returns, contains the number of valid entries written to <paramref ///
/// name="node" />. The value must not exceed <paramref name="node" />.Length.
/// </param>
/// <returns>
/// <see langword="true" /> if any prediction data was produced; otherwise, <see langword="false"
/// />.
/// </returns>
bool Predict(Span<CacheLinePrediction> node, out int count);
bool Predict(
Span<CacheLinePrediction> node,
out int count
);
/// <summary>
/// Materializes the cache line identified by <paramref name="origin" /> into <paramref
/// Materializes the cache line identified by <paramref name="origin" /> into <paramref ///
/// name="cache" />.
/// </summary>
/// <param name="origin">
@@ -65,7 +70,11 @@ namespace StgSharp.HighPerformance.Memory
/// <param name="cache">
/// Destination cache line buffer.
/// </param>
void Prefetch(nuint origin, ulong policy, Span<byte> cache);
void Prefetch(
nuint origin,
ulong policy,
Span<byte> cache
);
/// <summary>
/// Writes the cache line in <paramref name="cache" /> back to <paramref name="origin" />.
@@ -79,21 +88,29 @@ namespace StgSharp.HighPerformance.Memory
/// <param name="cache">
/// Source cache line buffer.
/// </param>
void WriteBack(nuint origin, ulong policy, ReadOnlySpan<byte> cache);
void WriteBack(
nuint origin,
ulong policy,
ReadOnlySpan<byte> cache
);
}
public struct CacheLinePrediction : IEquatable<CacheLinePrediction>
{
public override readonly bool Equals(object? obj)
public override readonly bool Equals(
object? obj
)
{
return obj is CacheLinePrediction prediction &&
Address.Equals(prediction.Address) &&
MapPolicy == prediction.MapPolicy;
}
public readonly bool Equals(CacheLinePrediction other)
public readonly bool Equals(
CacheLinePrediction other
)
{
return
Address == other.Address && MapPolicy == other.MapPolicy;
@@ -104,11 +121,17 @@ namespace StgSharp.HighPerformance.Memory
return HashCode.Combine(Address, MapPolicy);
}
public static bool operator !=(CacheLinePrediction left, CacheLinePrediction right)
public static bool operator !=(
CacheLinePrediction left,
CacheLinePrediction right
)
{
return !(left == right);
}
public static bool operator ==(CacheLinePrediction left, CacheLinePrediction right)
public static bool operator ==(
CacheLinePrediction left,
CacheLinePrediction right
)
{
return left.Equals(right);
}
StgSharp.Common/HighPerformance/Memory/L4.Prefetch.cs
+4 -2
View File
@@ -43,7 +43,9 @@ namespace StgSharp.HighPerformance.Memory
throw new OverflowException("Too many activated cache line in external reference.");
}
Span<CacheLinePrediction> span = new(_prediction, PredictionCount);
if (!(PrefetchPredict.Predict(span, out int actualCount) && actualCount > 0)) {
if (!PrefetchPredict.Predict(span, out int actualCount) && (actualCount <= 0))
{
_exhausted = true;
return;
}
int missIndex = 0;
@@ -85,7 +87,7 @@ namespace StgSharp.HighPerformance.Memory
head->_origin = address;
head->_profile = handle.MapPolicy;
head->_refCount = 0;
head->_address = (nuint)(&_data[index]);
head->_address = nuint & _data[index];
// pre fetch them here
PrefetchPredict.Prefetch(head->_origin, head->_profile, new Span<byte>((byte*)head->_address, Unsafe.SizeOf<CacheLineData>()));
StgSharp.Common/HighPerformance/Memory/L4.cs
+54 -45
View File
@@ -39,7 +39,6 @@ namespace StgSharp.HighPerformance.Memory
private const int PredictionLeastAhead = 1024;
private readonly CacheLineData* _data;
private readonly EvictionArray* _eviction;
private readonly CacheLineHead* _head;
private readonly CacheLinePrediction* _prediction;
@@ -57,12 +56,12 @@ namespace StgSharp.HighPerformance.Memory
public L4()
{
// init order is fallow by align requirement of each component.
nuint cacheSize = (nuint)Unsafe.SizeOf<CacheLineData>() * CacheLineCount; // SIMDID, no less than 16 byte bit
nuint entrySize = (nuint)Unsafe.SizeOf<CacheLineHead>() * CacheLineCount; // 16 byte align
nuint predictionSize = (nuint)Unsafe.SizeOf<CacheLinePrediction>() * PredictionCount; //16 byte align
nuint cacheSize = ((nuint)Unsafe.SizeOf<CacheLineData>()) * CacheLineCount; // SIMDID, no less than 16 byte bit
nuint entrySize = ((nuint)Unsafe.SizeOf<CacheLineHead>()) * CacheLineCount; // 16 byte align
nuint predictionSize = ((nuint)Unsafe.SizeOf<CacheLinePrediction>()) * PredictionCount; //16 byte align
nuint mapSize = (nuint)SwissTable.RequestedNativeMemorySize; // 16 byte align
nuint rrpvSize = (nuint)Unsafe.SizeOf<EvictionArray>(); // 16 byte align
nuint stackSize = (nuint)sizeof(int) * CacheLineCount; // int align
nuint stackSize = ((nuint)sizeof(int)) * CacheLineCount; // int align
// malloc all memory at once, and free at once in Dispose.
// This is to avoid fragmentation and improve performance.
@@ -85,7 +84,17 @@ namespace StgSharp.HighPerformance.Memory
ptr += stackSize;
}
public IPrefetchPredict PrefetchPredict { get; set; }
public IL4Predict PrefetchPredict { get; set; }
[MethodImpl(MethodImplOptions.AggressiveInlining)]
public void ContinueOnce(
L4CacheLine line
)
{
if (line.Address > 0) {
_ = Interlocked.Decrement(ref _aheadCount);
}
}
[System.Diagnostics.CodeAnalysis.SuppressMessage(
"Design",
@@ -108,11 +117,11 @@ namespace StgSharp.HighPerformance.Memory
}
[MethodImpl(MethodImplOptions.AggressiveInlining)]
public CacheLine Map(
nuint origin
public L4CacheLine Map(
nuint origin
)
{
if (_aheadCount < PredictionLeastAhead)
if ((_aheadCount < PredictionLeastAhead) && !PrefetchPredict.IsExhausted)
{
if (Interlocked.CompareExchange(ref _prefetching, 1, 0) == 0)
{
@@ -141,7 +150,7 @@ namespace StgSharp.HighPerformance.Memory
(*_eviction)[entry->_id] = 0;
_ = Interlocked.Increment(ref _activeCount);
_ = Interlocked.Decrement(ref _aheadCount);
return new CacheLine(entry->_address, ref _activeCount, ref entry->_refCount);
return new L4CacheLine(entry->_address, ref _activeCount, ref entry->_refCount);
} else
{
_ = Interlocked.Decrement(ref entry->_refCount);
@@ -157,41 +166,6 @@ namespace StgSharp.HighPerformance.Memory
nuint origin
);
public ref struct CacheLine : IDisposable
{
private ref int _activeCount;
private ref int _refCount;
private nuint _handle;
internal CacheLine(
nuint handle,
ref int activeCount,
ref int cacheRefCount
)
{
_handle = handle;
_refCount = ref cacheRefCount;
_activeCount = ref activeCount;
}
[Obsolete("You should not create a CacheLineHandle outside a L4", true)]
public CacheLine() { }
public nuint Address => _handle;
public void Dispose()
{
if (_handle == 0) {
return;
}
_handle = 0;
_ = Interlocked.Decrement(ref _activeCount);
_ = Interlocked.Decrement(ref _refCount);
}
}
private struct CacheLineData
{
@@ -200,4 +174,39 @@ namespace StgSharp.HighPerformance.Memory
}
}
public ref struct L4CacheLine : IDisposable
{
private ref int _activeCount;
private ref int _refCount;
private nuint _handle;
internal L4CacheLine(
nuint handle,
ref int activeCount,
ref int cacheRefCount
)
{
_handle = handle;
_refCount = ref cacheRefCount;
_activeCount = ref activeCount;
}
[Obsolete("You should not create a CacheLineHandle outside a L4", true)]
public L4CacheLine() { }
public readonly nuint Address => _handle;
public void Dispose()
{
if (_handle == 0) {
return;
}
_handle = 0;
_ = Interlocked.Decrement(ref _activeCount);
_ = Interlocked.Decrement(ref _refCount);
}
}
}